Programming methods and memories
Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.
1. A method of programming a memory, comprising:
boosting a channel voltage while applying a first portion of a plurality of programming pulses to a selected access line until a first voltage level of the channel voltage occurs when a final program pulse of the first portion of the plurality of programming pulses is applied; and
when a criteria is met, boosting the channel voltage while applying a second portion of the plurality of programming pulses to the selected access line, starting from a second voltage level of the channel voltage that occurs when an initial program pulse of the second portion of the plurality of programming pulses is applied;
wherein the second voltage level of the channel voltage that occurs when the initial program pulse of the second portion of the plurality of programming pulses is applied is less than the first voltage level of the channel voltage that occurs when the final program pulse of the first portion of the plurality of programming pulses is applied.
2. The method of claim 1 , wherein boosting the channel voltage comprises applying a voltage to an unselected access line.
3. The method of claim 2 , further comprising grounding an access line on either side of the unselected access line while applying the voltage to the unselected access line.
4. The method of claim 1 , further comprising, when the criteria is met, shifting a voltage applied to an unselected access line from a voltage level of the voltage applied to the unselected access line that occurs when the final program pulse of the first portion of the plurality of programming pulses is applied to a lower voltage level of the voltage applied to the unselected access line that occurs when the initial program pulse of the second portion of the plurality of programming pulses is applied.
5. The method of claim 1 , wherein the first portion of the plurality of programming pulses are applied in a region of the memory having a pattern in which data lines immediately adjacent to and on each side of an inhibited data line are not inhibited is dominant in the memory.
6. The method of claim 1 , wherein the second portion of the plurality of programming pulses are applied in a region of the memory where a majority of cells being inhibited are connected to data lines having immediately adjacent data lines on each side thereof inhibited.
7. The method of claim 1 , wherein the criteria is a determined number of programming pulses.
8. The method of claim 1 , wherein the criteria is a determined average threshold voltage of the cells being programmed.
9. The method of claim 1 , wherein the criteria is completion of a determined level of programming.
10. The method of claim 1 , wherein the criteria is dominance of a CS0 pattern over a CS2 pattern.
11. The method of claim 1 , wherein programming the memory comprises programming a single page of the memory, wherein the criteria is a certain point in the programming of the single page of the memory.
12. A memory device, comprising:
control circuitry;
wherein the control circuitry is configured to boost a channel voltage while a first portion of a plurality of programming pulses is applied to a selected access line until a first voltage level of the channel voltage occurs when a final program pulse of the first portion of the plurality of programming pulses is applied;
wherein the control circuitry is configured, when a criteria is met, to boost the channel voltage while applying a second portion of the plurality of programming pulses to the selected access line, starting from a second voltage level of the channel voltage that occurs when an initial program pulse of the second portion of the plurality of programming pulses is applied; and
wherein the second voltage level of the channel voltage that occurs when the initial program pulse of the second portion of the plurality of programming pulses is applied is less than the first voltage level of the channel voltage that occurs when the final program pulse of the first portion of the plurality of programming pulses is applied.
13. The memory device of claim 12 , wherein the control circuitry being configured to boost the channel voltage comprises the control circuitry being configured to apply a voltage to an unselected access line.
14. The memory device of claim 13 , wherein the control circuitry is configured to ground an access line on either side of the unselected access line while the voltage is applied to the unselected access line.
15. The memory device of claim 12 , wherein the control circuitry is configured to shift a voltage applied to an unselected access line from a voltage level of the voltage applied to the unselected access line that occurs when the final program pulse of the first portion of the plurality of programming pulses is applied to a lower voltage level of the voltage applied to the unselected access line that occurs when the initial program pulse of the second portion of the plurality of programming pulses is applied.
16. The memory device of claim 12 , wherein the criteria is a certain point during programming of a single page of the memory device.
17. A method of programming a memory, comprising:
boosting a channel voltage while applying a first portion of a plurality of programming pulses to a selected access line until a first voltage level of the channel voltage occurs when a final program pulse of the first portion of the plurality of programming pulses is applied; and
when a criteria is met, boosting the channel voltage while applying a second portion of the plurality of programming pulses to the selected access line, starting from a second voltage level of the channel voltage that occurs when an initial program pulse of the second portion of the plurality of programming pulses is applied;
wherein the second voltage level of the channel voltage that occurs when the initial program pulse of the second portion of the plurality of programming pulses is applied is less than the first voltage level of the channel voltage that occurs when the final program pulse of the first portion of the plurality of programming pulses is applied; and
wherein a difference between a voltage level of the final program pulse of the first portion of the plurality of programming pulses and the first voltage level of the channel voltage is the same as a difference between a voltage level of the initial program pulse of the second portion of the plurality of programming pulses and the second voltage level of the channel voltage.
18. The method of claim 17 , further comprising:
applying a first portion of a plurality of inhibit pulses to a plurality of unselected access lines while applying the first portion of the plurality of programming pulses to the selected access line; and
applying a second portion of the plurality of inhibit pulses to the plurality of unselected access lines while applying the second portion of the plurality of programming pulses to the selected access line.
19. The method of claim 18 , wherein a voltage level of an inhibit pulse of the first portion of the plurality of inhibit pulses that occurs when the final program pulse of the first portion of the plurality of programming pulses is applied is greater than a voltage level of an inhibit pulse of the second portion of the plurality of inhibit pulses that occurs when the initial program pulse of the second portion of the plurality of programming pulses is applied.
20. The method of claim 17 , wherein the first portion of the plurality of programming pulses are applied in a region of the memory having a pattern in which data lines immediately adjacent to and on each side of an inhibited data line are not inhibited is dominant in the memory, and wherein the second portion of the plurality of programming pulses are applied in a region of the memory where a majority of cells being inhibited are connected to data lines having immediately adjacent data lines on each side thereof inhibited.