Apparatuses and methods for reducing off state leakage currents

1. An apparatus, comprising:

a switch having an input node and an output node, wherein the switch is configured to couple a signal on the input node to the output node when the switch is in an on state and further configured to decouple the input and output nodes when the switch is in an off state, and wherein the switch comprises:

first and second transistors, each having gate, source and drain electrodes, wherein the first and second transistors are configured to be in an off state when the switch is in the off state based on a high reference voltage coupled to the gate of the first transistor and a low reference voltage coupled to the gate of the second transistor; and

third and fourth transistors, each having gate, source and drain electrodes, wherein the third and fourth transistors are configured to be in a first conductive state when the switch is in the off state based on an intermediate voltage coupled to the gates of the third and fourth transistors, wherein the intermediate voltage is less than the high reference voltage and greater than the low reference voltage, wherein the third and fourth transistors are configured to be in a second conductive state when the switch is in the on state based on the low reference voltage coupled to the gate of the third transistor and the high reference voltage coupled to the gate of the fourth transistor,

wherein the drain electrode of the first transistor is coupled to the source electrode of the third transistor, the drain electrode of the second transistor is coupled to the source electrode of the fourth transistor, and wherein the drain electrodes of the third and fourth transistors are coupled together to the output node.

2. The apparatus of claim 1 , wherein source electrodes of the first and second transistors are coupled together to the input node, and wherein gate electrodes of the first and second transistors are selectively provided a low reference voltage and a high reference voltage, respectively, to cause the first and second transistors to be in the off state.

3. The apparatus of claim 2 , wherein the first and second transistors form a pass gate.

4. The apparatus of claim 1 , wherein the third and fourth transistors are cascode coupled with the first and second transistors, respectively.

5. The apparatus of claim 1 , wherein the source electrodes of the first and second transistors are coupled to high and low reference voltages, respectively, and gate electrodes of the first and second transistors are selectively provided a low reference voltage and a high reference voltage, respectively, to cause the first and second transistors to be in the off state.

6. The apparatus of claim 5 , wherein the first, second, third and fourth transistors form a first high impedance inverter.

7. The apparatus of claim 6 , further comprising:

an inverter having an input and an output, wherein the input of the inverter is coupled to the input node;

a second high impedance inverter having an input and an output, wherein the input is coupled to the output of the inverter;

a voltage source coupled to the gates of the third and fourth transistors, wherein the voltage source is configured to provide the intermediate voltage when the switch is in the off state, and further configured to be in a high impedance state when the switch is in the on state, and

wherein the gates of the third and fourth are further coupled to the output of the second high impedance inverter.

8. A switch, comprising:

a first pass gate comprising a first PMOS transistor and a first NMOS transistor, wherein a source electrode of the first PMOS transistor is coupled to an input of the first pass gate, and a source electrode of the first NMOS transistor is coupled to the input of the first pass gate, a drain electrode of the first PMOS transistor is coupled to a first intermediate node, and a drain electrode of the first NMOS transistor is coupled to a second intermediate node, and wherein, when the switch is in the off state, a gate electrode of the first PMOS transistor is selectively provided a first reference voltage and a gate electrode of the first NMOS transistor is selectively provided a second reference voltage; and

a second pass gate comprising a second PMOS transistor and a second NMOS transistor, wherein a source electrode of the second PMOS transistor is coupled to the first intermediate node, and a source of the second NMOS transistor is coupled to the second intermediate node, and drain electrodes of the second PMOS and NMOS transistors are coupled to an output of the second pass gate, and wherein, when the switch is in the off state, gate electrodes of the second PMOS and NMOS transistors are selectively provided a third reference voltage, wherein the third reference voltage is less than the first reference voltage and greater than the second reference voltage, wherein, when the switch is in the on state, the gate electrode of the second NMOS transistor is selectively provided the first reference voltage and the gate electrode of the second PMOS transistor is selectively provided the second reference voltage.

9. The switch of claim 8 , wherein the second pass gate is cascode coupled to the first pass gate.

10. The switch of claim 8 , wherein the first pass gate is in an on state when the gate electrode of the first PMOS transistor is coupled to a low reference voltage, and the gate electrode of the first NMOS transistor is coupled to a high reference voltage.

11. The switch of claim 8 , wherein the second reference voltage is equal to the low reference voltage, and the second reference voltage is equal to the highreference voltage.

12. The switch of claim 11 , wherein the switch is in the on state when both the first and second pass gates are in the on state.