IP Library Granted Patent US 9,830,955
Granted Patent B2
US 9,830,955 · App. 15/251,770 · Granted Nov 28, 2017

Data shifting

Inventors: Timothy B. Cowles (Boise, ID); Steven M. Bodily (Boise, ID)
Assignee: Micron Technology, Inc.
G11C7/065G11C5/06G11C7/06G11C7/08G11C7/1036G11C7/22G11C8/10G11C11/4091G11C19/00G11C2207/002G11C2207/005
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Quick Facts
Patent No.
US 9,830,955
App. No.
15/251,770
Granted
Nov 28, 2017
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

Claims (51)

1. A method, comprising:

shifting a plurality of data values stored in a respective plurality of memory cells coupled to a selected access line and to respective first sense lines, wherein the shifting comprises:

enabling respective first devices coupled between the respective plurality of memory cells and respective sensing circuitries, and activating the respective sensing circuitries to store the plurality of data values in the respective sensing circuitries;

disabling the respective first devices coupled between the respective plurality of memory cells and the respective sensing circuitries to decouple the respective first sense lines from the respective sensing circuitries; and

to shift data in a first direction, activating the selected access line and enabling respective second devices coupled between the respective sensing circuitries and respective memory cells coupled to respective second sense lines adjacent the first sense lines in the first direction; and

to shift data in a second direction, activating the selected access line and enabling respective third devices coupled to respective third sense lines adjacent the first sense lines in the second direction;

wherein the second devices each comprise:

a first node coupled to a first node of a respective first device coupled to a respective first sense line; and

a second node coupled to a second node of a respective first device coupled to a respective second sense line in the first direction; and

wherein the third devices each comprise:

a first node coupled to the first node of the respective first device coupled to the respective first sense line; and

a second node coupled to a second node of a respective first device coupled to a respective third sense line in the second direction.

2. The method of claim 1 , wherein the first sense lines are each one of respective pairs of complementary sense lines, and wherein transferring the plurality of data values to the respective adjacent sensing circuitries comprises latching the plurality of data values in respective sense amplifiers coupled to respective adjacent complementary sense line pairs.

3. An apparatus, comprising:

an array of memory cells; and

a controller coupled to the array and configured to use sensing circuitry to:

perform a first sensing operation comprising:

activating a selected access line to which a plurality of memory cells are coupled, wherein the plurality of memory cells are coupled to respective sense lines; and

while the selected access line is activated, transferring respective data values stored in the plurality of memory cells to respective first sensing circuitries via the respective sense lines; and

separately from the first sensing operation, perform a data shifting operation by:

activating the selected access line to which the plurality of memory cells are coupled; and

while the selected access line is activated, transferring the respective data values stored in the respective first sensing circuitries from the respective first sensing circuitries to respective sensing circuitries different from the first sensing circuitries and selectively coupled thereto by at least one of:

enabling respective first devices configured to selectively couple the plurality of sense lines to the respective different sensing circuitries in a first direction; and

enabling respective second devices configured to selectively couple the plurality of sense lines to respective different sensing circuitries in a second direction.

4. The apparatus of claim 3 , wherein the respective first devices are transistors each having a first node coupled to one of the respective plurality of sense lines and a second node coupled to one of the respective different sense lines, and wherein the respective second devices are transistors each having a first node coupled to the first node of one of the respective first devices.

5. The apparatus of claim 3 , wherein each of the first sensing circuitries comprises a sense amplifier and an accumulator.

6. The apparatus of claim 3 , wherein each of plurality of sense lines are one of a respective plurality of complementary sense line pairs.

7. An apparatus, comprising:

an array of memory cells comprising:

a first memory cell coupled to a first sense line;

a second memory cell coupled to a second sense line;

a first device configured to selectively couple the first sense line to a first sensing circuitry responsive to a first control signal applied to the first device;

a second device configured to selectively couple the first sense line to a second sensing circuitry responsive to a second control signal applied to the second device;

a third device configured to selectively couple the first sense line to a third sensing circuitry responsive to a third control signal applied to the third device; and

a controller configured to:

control the first device and the second device via the first control signal and the second control signal to shift data in a first direction in the array; and

control the first device and the third device via the first control signal and the third control signal to shift data in a second direction in the array.

8. The apparatus of claim 7 , wherein the controller is configured to control shifting of data in the array by enabling the second device via the second control signal while disabling the first device via the first control signal in order to transfer a data value stored in the first memory cell to the second sensing circuitry.

9. The apparatus of claim 8 , wherein the controller is further configured to control shifting of data in the array by transferring the data value stored in the first memory cell to the second sensing circuitry without first storing the data value in the first sensing circuitry.

10. The apparatus of claim 9 , wherein the first sense line is one of a first complementary sense line pair corresponding to a first column of the array, and the second sense line is one of a second complementary sense line pair corresponding to a second column of the array, and wherein the first column is adjacent to the second column.

11. The apparatus of claim 10 , wherein:

the first device comprises:

a first node coupled to an access device of the first memory cell; and

a second node coupled to an input node of a sense amplifier of the first sensing circuitry; and

the second device comprises:

a first node coupled to the access device of the first memory cell; and

a second node coupled to an input node of a sense amplifier of the second sensing circuitry.

12. The apparatus of claim 11 , wherein the first device is a transistor having a gate configured to receive the first control signal, and wherein the second device is a transistor having a gate configured to receive the second control signal.

13. The apparatus of claim 7 , wherein at least one of the first sensing circuitry and the second sensing circuitry comprises a sense amplifier and an accumulator.

14. The apparatus of claim 7 , wherein the array of memory cells further comprises:

a third memory cell coupled to the third sense line, wherein the first sense line is located between the second sense line and the third sense line.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2016
From: COWLES, TIMOTHY B.; BODILY, STEVEN M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039588/0381 →
Continuity (3)
Continuation 14660219 · Mar 17, 2015
Continuation 14031432 · Sep 19, 2013
Related Publication 20160372165A1 · Dec 22, 2016