Semiconductor device including semiconductor chips mounted over both surfaces of substrate
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30 , a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30 , a sealing resin 71 covering the semiconductor chip 10 , a sealing resin 72 covering the semiconductor chip 20 , a plurality of conductive posts provided to penetrate through the sealing resin 72 , and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30 , and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.
1. A semiconductor device comprising:
an insulating base material comprising a first main surface and a second main surface opposite to the first main surface;
a plurality of first connection pads formed on the first main surface;
a plurality of second connection pads formed on the second main surface;
a first semiconductor chip comprising a main surface on which a plurality of first pad electrodes are provided, the first semiconductor chip mounted over the first main surface of the insulating base material so that the main surface of the first semiconductor chip faces the first main surface of the insulating base material and that the plurality of first pad electrodes are placed between the main surface of the first semiconductor chip and the first main surface of the insulating base material, each of the first pad electrodes being electrically connected to a corresponding one of the first connection pads;
a first sealing resin provided over the first main surface of the insulating base material;
a second semiconductor chip comprising a main surface on which a plurality of second pad electrodes are provided, the second semiconductor chip mounted over the second main surface of the insulating base material so that the main surface of the second semiconductor chip faces the second main surface of the insulating base material and that the plurality of second pad electrodes are placed between the main surface of the second semiconductor chip and the second main surface of the insulating base material, each of the second pad electrodes being electrically connected to a corresponding one of the second connection pads;
a second sealing resin provided over the second main surface of the insulating base material; and
a plurality of external terminals provided on the second main surface of the insulating base material so as to expose from the second sealing resin.
2. The semiconductor device as claimed in claim 1 , further comprising:
a first underfill material provided between the insulating base material and the first semiconductor chip; and
a second underfill material provided between the insulating base material and the second semiconductor chip.
3. The semiconductor device as claimed in claim 1 ,
wherein the first semiconductor chip further comprises a plurality of first bump electrodes thereon, each of the first bump electrodes being coupled to an associated one of the first connection pads and associated one of the first pad electrodes of the first semiconductor chip; and
wherein the second semiconductor chip further comprises a plurality of second bump electrodes thereon, each of the second bump electrodes being coupled to an associated one of the second connection pads and an associated one of the second pad electrodes of the second semiconductor chip.
4. The semiconductor device as claimed in claim 1 , wherein the second semiconductor chip further comprises a plurality of second bump electrodes thereon, each of the second bump electrodes being coupled to an associated one of the second connection pads and an associated one of the second pad electrodes of the second semiconductor chip.
5. The semiconductor device as claimed in claim 1 , wherein at least one of a coefficient of linear expansion and a shrinkage ratio of the second sealing resin is greater than that of the first sealing resin.
6. The semiconductor device as claimed in claim 1 , wherein a thickness of the second sealing resin is thicker than that of the first sealing resin.
7. The semiconductor device as claimed in claim 2 , wherein at least one of a coefficient of linear expansion and a shrinkage ratio of the second underfill material is greater than that of the first underfill material.
8. The semiconductor device as claimed in claim 1 , wherein each of the external terminals comprises a conductive post penetrating the second sealing resin and a solder ball mounted on the conductive post.
9. The semiconductor device as claimed in claim 1 ,
wherein the main surface of the first semiconductor chip is defined with a rectangular constituted by first sides and second sides shorter than the first sides;
wherein the main surface of the second semiconductor chip is defined with a rectangular constituted by third sides and fourth sides shorter than the third sides, the second semiconductor chip being mounted over the second main surface of the insulating base material so that the third sides of the second semiconductor chip is perpendicular to the first sides of the first semiconductor chip;
wherein the first pad electrodes are arranged along the second sides of the first semiconductor chip; and
wherein the second pad electrodes are arranged along the fourth sides of the second semiconductor chip.
10. The semiconductor device as claimed in claim 1 , wherein the second semiconductor chip further comprises a bottom surface opposite to the main surface, the bottom surface being covered with the second sealing resin.
11. The semiconductor device as claimed in claim 1 , wherein each of the first and second semiconductor chips is a memory chip.
12. The semiconductor device as claimed on claim 8 ,
wherein the second sealing resin comprises a bottom surface that faces away from the insulating base material;
wherein each of the conductive posts comprises an exposed surface that is substantially coplanar with the bottom surface of the second sealing resin; and
wherein each of the solder balls is mounted on an associated one of the exposed surface of the conductive posts.
13. A semiconductor device comprising:
a wiring structure comprising:
an insulating layer including a first surface and a second surface opposite to the first surface;
a plurality of first wiring patterns formed on the first surface of the insulating layer, each of the plurality of first wiring patterns including a first connection pad;
a plurality of second wiring patterns formed on the second surface of the insulating layer, each of the plurality of second wiring patterns including a second connection pad and a first land; and
a plurality of third wiring patterns formed on the second surface of the insulating layer, each of the plurality of third wiring pattern including a second land,
wherein each of the plurality of third wiring pattern is electrically connected to an associated one of the plurality of first wiring patterns;
a first semiconductor chip comprising:
a third surface; and
a plurality of first electrodes formed on the third surface;
wherein the first semiconductor chip is disposed over the wiring structure so that the third surface of the first semiconductor chip faces the first surface of the insulating layer with a flip-chip bonding between each of the plurality of first electrodes and the first connection pad of an associated one of the plurality of first wiring patterns;
a second semiconductor chip comprising:
a fourth surface; and
a plurality of second electrodes formed on the fourth surface;
wherein the second semiconductor chip is disposed under the wiring structure so that the fourth surface of the second semiconductor chip faces the second surface of the insulating layer with a flip-chip bonding between each of the plurality of second electrodes and the second connection pad of an associated one of the plurality of second wiring patterns;
a sealing resin provided on a side of the second surface of the insulating layer, wherein the sealing resin covers the plurality of second wiring patterns and the plurality of third wiring patterns in contact with the second semiconductor chip;
a plurality of first conductive posts, wherein each of the first plurality of conductive posts is in an electrical contact with the first land of an associated one of the plurality of second wiring patterns and penetrates through the sealing resin to form a first end portion exposed from the sealing resin; and
a plurality of second conductive posts, wherein each of the second plurality of conductive posts is in an electrical contact with the second land of an associated one of the plurality of third wiring patterns and penetrates through the sealing resin to form a second end portion exposed from the sealing resin.
14. The device of claim 13 , wherein the wiring structure further comprises a plurality of through-hole conductors, and each of the through-hole conductors is provided in the insulating layer to electrically connect an associated one of the plurality of third wiring patterns to an associated one of the plurality of first wiring patterns.
15. The device of claim 13 , further comprising an additional sealing resin provided on a side of the first surface of the insulating layer, wherein the additional sealing resin covers the plurality of first wiring patterns in contact with the second semiconductor chip.
16. The device of claim 15 , wherein the sealing resin covers the second semiconductor ship and the additional sealing resin covers the first semiconductor chip.
17. The device of claim 13 , wherein each of first and second semiconductor chips has a rectangular shape defined by a pair of longer sides and a pair of shorter sides, and the pair of longer sides of the first semiconductor chip cross the pair of longer sides of the second semiconductor chip.
18. The device of claim 13 , wherein each of the first electrodes of the first semiconductor chip comprises a first pad electrode and a first bump electrode formed on the pad electrode, and each of the second electrodes of the second semiconductor chip comprises a second pad electrode and a second bump electrode formed on the pad electrode.
19. The device of claim 18 , wherein the flip-chip bonding includes a solder connection between the first bump electrode and the first connection pad and between the second bump electrode and the second connection pad.
20. The device of claim 13 , further comprising a plurality of first solder balls and a plurality of second solder balls, wherein each of the first solder balls is provided on the first end portion of an associated one of the plurality of first conductive posts, and wherein each of the second solder balls is provided on the second end portion of an associated one of the plurality of second conductive posts.