IP Library Granted Patent US 10,504,881
Granted Patent B2
US 10,504,881 · App. 15/229,651 · Granted Dec 10, 2019

Stacked semiconductor die assemblies with support members and associated systems and methods

Inventors: Hong Wan Ng (Singapore, SG); Seng Kim Ye (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L25/50H01L23/3128H01L24/33H01L24/49H01L24/83H01L24/85H01L25/0657H01L25/18H01L24/48H01L2224/04042H01L2224/05554H01L2224/05599H01L2224/06135H01L2224/32145H01L2224/32225H01L2224/33181H01L2224/48227H01L2224/49171H01L2224/73265H01L2224/8385H01L2224/83191H01L2224/83201H01L2224/85399H01L2224/92247H01L2225/0651H01L2225/06555H01L2225/06562H01L2225/06593H01L2924/00014H01L2924/01014H01L2924/1033H01L2924/10253H01L2924/1205H01L2924/143H01L2924/1434H01L2924/1436H01L2924/1437H01L2924/1438H01L2924/15174H01L2924/15182H01L2924/15184H01L2924/15311H01L2924/181H01L2924/182H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105
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Quick Facts
Patent No.
US 10,504,881
App. No.
15/229,651
Granted
Dec 10, 2019
Kind
B2
Abstract

Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

Claims (38)

1. A method of manufacturing a semiconductor die assembly, the method comprising:

attaching a first semiconductor die to a package substrate;

positioning a first support member and a second support member on opposite sides of the first semiconductor die, wherein the first support member is substantially parallel to the second support member, and wherein the first support member is flush with a first border of a footprint of a second semiconductor die and the second support member is flush with a second border of the footprint of the second semiconductor die;

positioning a third support member that is substantially perpendicular to the first and second support members, wherein the third support member is positioned wholly within the footprint of the second semiconductor die and set back from a closest border of the footprint of the second semiconductor die by a distance, and wherein the third support member is spaced apart from each of the first and second support members by a gap;

attaching the second semiconductor die to the first, second, and third support members via a die-attach film such that (a) the first, second, and third support members carry the second semiconductor die above the first semiconductor die and (b) the first, second, and third support members, the second semiconductor die; and

flowing an encapsulant into the cavity through the gap to at least partially provide mechanical support for the second semiconductor die.

2. The method of claim 1 , further comprising:

wirebonding first bond pads of the package substrate to corresponding bond pads of the first semiconductor die; and

wirebonding second bond pads of the package substrate to corresponding bond pads of the second semiconductor die,

wherein the first bond pads are within the footprint of the second semiconductor die.

3. The method of claim 1 wherein the die-attach film is a first die-attach film, and wherein attaching the first semiconductor die to the package substrate includes attaching the first semiconductor die to the package substrate with a second die-attach film.

4. The method of claim 1 wherein the die-attach film is a first die-attach film, and wherein positioning the first support member and the second support member includes:

attaching the first support member to the package substrate with a second die-attach film; and

attaching the second support member to the package substrate with a third die-attach film.

5. The method of claim 1 wherein the die-attach film does not attach the first semiconductor die to the second semiconductor die.

6. The method of claim 5 , further comprising forming wirebonds that electrically couple the first semiconductor die with the package substrate, wherein a portion of the wirebonds projects into the die-attach film.

7. A method of manufacturing a semiconductor die assembly, the method comprising:

attaching a first semiconductor die to a package substrate;

positioning a first support member and a second support member on opposite sides of the first semiconductor die, wherein the first support member is substantially parallel to the second support member, and wherein the first support member is flush with a first border of a footprint of a second semiconductor die and the second support member is flush with a second border of the footprint of the second semiconductor die, wherein positioning the first support member and the second support member includes—

covering a semiconductor wafer with a die-attach material;

cutting the semiconductor wafer to form elongate semiconductor members each having a portion of the die-attach material attached thereto; and

attaching the elongate semiconductor members to the package substrate via the portion of the die-attach material attached to each of the elongate semiconductor members;

positioning a third support member that is substantially perpendicular to the first and second support members, wherein the third support member is positioned wholly within the footprint of the second semiconductor die and set back from a closest border of the footprint of the second semiconductor die by a distance, and wherein the third support member is spaced apart from each of the first and second support members by a gap;

attaching the second semiconductor die to the first, second, and third support members such that the first, second, and third support members carry the second semiconductor die above the first semiconductor die;

forming wirebonds electrically coupling bond pads of the package substrate to corresponding bond pads of the second semiconductor die; and

attaching a third semiconductor die to the second semiconductor die via an over-wire material, wherein a portion of the wirebonds extend into the over-wire material.

8. The method of claim 1 , further comprising coupling first bond pads of the package substrate to corresponding second bond pads of the first semiconductor die with wirebonds, wherein the first bond pads are within the footprint of the second semiconductor die, and wherein attaching the second semiconductor die includes attaching the second semiconductor die to the first, second, and third support members via the die-attach film such that the wirebonds do not contact the die-attach film.

9. The method of claim 5 wherein the die-attach film has a uniform thickness.

10. The method of claim 1 , further comprising:

forming wirebonds electrically coupling bond pads of the package substrate to corresponding bond pads of the second semiconductor die; and

attaching a third semiconductor die to the second semiconductor die via an over-wire material, wherein a portion of the wirebonds extend into the over-wire material.

11. The method of claim 10 wherein—

the wirebonds are first wirebonds,

the bond pads of the package substrate are first bond pads,

the method further comprises forming second wirebonds electrically coupling second bond pads of the package substrate to corresponding bond pads of the first semiconductor die, and

a portion of the second wirebonds projects into the die-attach film.

12. The method of claim 11 wherein the die-attach material has a uniform first thickness, and wherein the over-wire material has a uniform second thickness, greater than the first thickness.

13. The method of claim 7 wherein the first, second, and third support members, the second semiconductor die, and the package substrate together define a cavity beneath the second semiconductor die, and wherein the method further includes flowing an encapsulant into the cavity through the gap to at least partially provide mechanical support for the second semiconductor die.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2016
From: NG, HONG WAN; YE, SENG KIM
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039386/0646 →
Continuity (2)
Division 14264584 · Apr 29, 2014
Related Publication 20160343699A1 · Nov 24, 2016