IP Library Granted Patent US 9,972,367
Granted Patent B2
US 9,972,367 · App. 15/216,440 · Granted May 15, 2018

Shifting data in sensing circuitry

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Quick Facts
Patent No.
US 9,972,367
App. No.
15/216,440
Granted
May 15, 2018
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

Claims (27)

1. A method, comprising:

enabling a first shift signal while a second shift signal is disabled to shift a data value from a first storage location to a second storage location associated with a compute component of a sensing circuitry;

disabling the first shift signal;

enabling the second shift signal while the first shift signal is disabled to shift the data value from the second storage location to a third storage location,

wherein the first storage location and the second storage location are associated with a first compute component and the third storage location is associated with a second compute component.

2. The method of claim 1 , further comprising sharing a charge between the first storage location and the second storage location of the compute component of the sensing circuitry by disabling the second shift signal in response to disabling the first shift signal.

3. The method of claim 2 , wherein sharing the charge comprises shorting a node associated with the first storage location to a node associated with the second storage location.

4. The method of claim 1 , further comprising:

enabling the first shift signal during a first clock cycle; and

disabling the first shift signal and enabling the second shift signal during a second clock cycle.

5. The method of claim 1 , further comprising:

applying a first voltage to the first storage location when the first shift signal is enabled; and

applying a second voltage to the second storage location when the second shift signal is enabled.

6. An apparatus, comprising:

sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith; and

a controller coupled to the sensing circuitry, wherein the controller is configured to:

enable a first shift signal while a second shift signal is disabled to shift a data value from the first storage location to the second storage location;

disable the first shift signal;

enable the second shift signal while the first shift signal is disabled to shift the data value from the second storage location to a third storage location.

7. The apparatus of claim 6 , wherein the first storage location and the second storage location are associated with a first compute component and the third storage location is associated with a second compute component.

8. The apparatus of claim 6 , wherein the controller is configured to:

enable the first shift signal during a first clock cycle; and

disable the first shift signal and enabling the second shift signal during a second clock cycle.

9. The apparatus of claim 6 , wherein the controller is configured to:

apply a first voltage to the first storage location when the first shift signal is enabled; and

apply a second voltage to the second storage location when the second shift signal is enabled.

10. The apparatus of claim 6 , wherein the controller is configured to cause a node associated with the first storage location to be shorted to a node associated with the second storage location in response to the first shift signal being disabled.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2016
From: PENNEY, DANIEL B.; VENKATA, HARISH N.; PERRY, GUY S.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039215/0587 →