Apparatuses Containing FinFETS
Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.
1 - 13 . (canceled)
14 . An apparatus comprising:
a plurality of finFETs, wherein each of the finFETs comprises a first pedestal serving as a first source/drain region, a second pedestal serving as a second source/drain region and a trough defining a channel region between the first and second source/drain region;
at least one bitline, wherein the at least one bitline extends to interconnect the first source/drain region of the plurality of finFETs to each other, wherein the at least one bitline comprises a plurality of first portions and a plurality of second portions, wherein each of the plurality of first portions is in contact with an associated one of the first source/drain region of the plurality of finFETs, wherein each of the plurality of second portions intervenes between corresponding adjacent two of the plurality of first portions, and wherein each the plurality of second portions comprises a first conductive material;
a plurality of storage devices; and
a plurality of contact plugs, wherein each of the plurality of contact plugs intervenes between an associated one of the plurality of storage devices and an associated one of the second source/drain region of the plurality of finFETs, wherein the each of the contact plugs comprises the first conductive material that is used in each of the plurality of second portions of the at least one bitline.
15 . The apparatus of claim 14 , wherein each of the plurality of first portions of the at least one bitline comprises the first conductive material that is used in each of the plurality of second portions of the at least one bitline and each of the plurality of contact plugs.
16 . The apparatus of claim 15 , wherein each of the plurality of first portions of the at least one bitline, each of the second portions of the at least one bitline and each of the contact plugs further comprise a second material, and wherein the first and second material are stacked with each other to provide a stacked conductive material.
17 . The apparatus of claim 16 , wherein each of the contact plugs further comprises a third conductive material, and wherein the third conductive material is between the stacked conductive material of an associated one of the plurality of contact plug and an associate done of the storage devices.
18 . The apparatus of claim 14 , further comprising a plurality of wordlines, wherein each of the plurality of wordlines being between corresponding adjacent two of the plurality of finFETs to overlap the channel region of at least one of the corresponding adjacent two of the plurality of finFETs with an intervention of gate dielectric material.
19 . The apparatus of claim 18 , wherein the at least one bitline crosses over each of the wordlines separately therefrom.
20 . The apparatus of claim 19 , wherein each of the storage devices comprises a capacitor, and wherein the capacitor comprises a lower electrode coupled to an associated one of the contact plugs, an upper electrode and dielectric material between the lower and upper electrodes.
21 . An apparatus comprising:
a conductive wordline extending along a first direction;
a rail of semiconductor material extending along the conductive wordline;
fins defined in the rail of semiconductor material, each fin having a first pedestal, a second pedestal, and a trough between the first and second pedestals;
digit lines electrically coupled with the second pedestals;
charge-storage devices electrically coupled with the first pedestals; and
a conductive beam extending beneath the conductive wordline.
22 . The apparatus of claim 21 wherein the conductive beam comprises a conductive material different from the conductive material of the conductive wordline.
23 . The apparatus of claim 21 wherein the conductive wordline is spaced from the conductive beam by dielectric material.
24 . The apparatus of claim 21 wherein the conductive wordline comprises metal, and wherein the conductive beam consists of conductively-doped silicon.
25 . The apparatus of claim 21 wherein the conductive wordline is one of a pair of conductive wordlines formed on opposing sides of the rail of semiconductor material.
26 . The apparatus of claim 21 wherein the rail of semiconductor material has a doped upper region and wherein said doped upper region becomes first source/drain regions in the first pedestals and second source/drain regions in the second pedestals.
27 . The apparatus of claim 21 wherein the charge-storage devices comprise capacitors.