Full bias sensing in a memory array
Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.
1. A method, comprising:
discharging, during a read operation, a charge from a first electrode between a capacitor of a memory cell and a selection component of the memory cell;
activating a switching component that couples a sensing capacitor to a latch that is coupled to a supply voltage that is lower than a supply voltage associated with the memory cell based at least in part on discharging the charge from the first electrode; and
determining a logic state of the memory cell based at least in part on activating the switching component.
2. The method of claim 1 , further comprising:
transferring, from the memory cell, a second charge to the sensing capacitor that is in electronic communication with a digit line of the memory cell after discharging the charge from the first electrode, wherein determining the logic state is based at least in part on transferring the second charge to the sensing capacitor.
3. The method of claim 2 , wherein transferring the second charge to the sensing capacitor comprises:
activating, after discharging the charge from the first electrode, a second switching component that couples the sensing capacitor with the digit line.
4. The method of claim 1 ,
wherein the supply voltage associated with the memory cell is for a group of memory cells that includes the memory cell.
5. The method of claim 1 , further comprising:
amplifying an output of the memory cell during a second time period, wherein the logic state of the memory cell is determined based at least in part on the amplified output.
6. The method of claim 1 , further comprising:
charging, during the read operation, an additional capacitor that is in electronic communication with a digit line.
7. The method of claim 1 , further comprising:
discharging, during the read operation, a third charge from a second electrode positioned between a second capacitor and a second selection component of a second memory cell that is in electronic communication with a digit line, wherein the memory cell and the second memory cell are coupled to a common access line.
8. A method, comprising:
charging, during a read operation, a capacitor that is in electronic communication with a memory cell via a digit line, wherein a charge transferred between the memory cell and the capacitor is based at least in part on a logic state of the memory cell;
coupling the capacitor with a latch that is in electronic communication with a first supply voltage different than a second supply voltage that is selectively coupled with a node of the capacitor; and
determining the logic state of the memory cell based at least in part on coupling the capacitor with the latch.
9. The method of claim 8 , further comprising:
selecting the memory cell for the read operation, wherein the memory cell is in electronic communication with the digit line, and wherein charging the capacitor is based at least in part on selecting the memory cell for the read operation.
10. The method of claim 8 , further comprising:
discharging, during the read operation and based at least in part on selecting the memory cell, a residual charge associated with the memory cell.
11. The method of claim 10 , wherein the memory cell is a first memory cell of a plurality of memory cells, and wherein the residual charge is associated with a prior access operation for at least one of the first memory cell or a second memory cell of the plurality of memory cells.
12. The method of claim 10 , wherein the memory cell includes a second capacitor coupled to a selection component via a middle electrode, and wherein the residual charge is stored at the middle electrode.
13. The method of claim 8 , wherein charging the capacitor comprises:
activating, during the read operation, a switching component that couples the capacitor to the memory cell via the digit line.
14. The method of claim 8 , wherein coupling the capacitor with the latch comprises:
activating a first switching component in electronic communication with the capacitor and the latch; and
isolating the capacitor from the second supply voltage coupled with the node of the capacitor, wherein the first supply voltage is less than the second supply voltage.
15. The method of claim 14 , wherein activating the first switching component comprises:
activating a second switching component to virtually ground the capacitor.
16. The method of claim 8 , further comprising:
charging a second capacitor that is in electronic communication with the capacitor and the latch, wherein the second capacitor is charged before the capacitor is charged.
17. The method of claim 16 , further comprising:
activating a switching component to couple the capacitor and the second capacitor to the latch, wherein the second capacitor is configured to modify a voltage output by the capacitor to the latch to a different value.
18. An apparatus, comprising:
a memory cell comprising a first capacitor, a selection component, and a first electrode coupled with the first capacitor and the selection component;
a second capacitor in electronic communication with the memory cell via a digit line;
a plurality of switching components in electronic communication with the second capacitor and a first voltage supply; and
a latch in electronic communication with the second capacitor and in electronic communication with a second voltage supply.
19. The apparatus of claim 18 , further comprising:
an amplifier positioned between the memory cell and the second capacitor, wherein the amplifier is configured to amplify an output signal of the memory cell.
20. The apparatus of claim 18 , wherein the second capacitor comprises a first terminal coupled to the digit line and to the first voltage supply via a first switching component of the plurality of switching components and a second terminal coupled to the first voltage supply via a second switching component of the plurality of switching components, wherein the second voltage supply is less than the first voltage supply.