Memory devices which include memory arrays
View Patent ↗Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.
1. A memory device comprising a memory array, wherein the memory array comprises:
a fin having a first source/drain region, a second source/drain region and a channel region between the first source/drain region and the second source/drain region; the first source/drain region extending to a first height; the second source/drain region extending to a second height less than the first height; the channel region extending along a trough between the first source/drain region and the second source/drain region;
a charge-storage device over the first source/drain region and electrically coupled with the first source/drain region;
a first sense/access line along a sidewall of the fin and spaced from the channel region by dielectric material; and
a second sense/access line over the second source/drain region and electrically coupled with the second source/drain region; an uppermost surface of the second sense/access line being beneath an uppermost surface of the first source/drain region.
2. The memory device of claim 1 wherein the second access/sense line comprises metal-containing material over conductively-doped semiconductor material.
3. The memory device of claim 1 wherein the charge-storage device is a capacitor.
4. The memory device of claim 1 wherein the first and second source/drain regions are p-type regions.
5. The memory device of claim 1 wherein the first and second source/drain regions are n-type regions.
6. The memory device of claim 3 wherein a portion of the capacitor extends to over the second access/sense line.
7. The memory device of claim 1 wherein the second access/sense line comprises metal and extends to a region peripheral to the memory array.
8. The memory device of claim 7 wherein the second access/sense line extends to sense amplifier circuitry within the region peripheral to the memory array.
9. The memory device of claim 7 wherein the second access/sense line extends to row driver circuitry within the region peripheral to the memory array.