Methods and apparatus for pattern matching using redundant memory elements
Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
1. A memory, comprising:
an array of memory cells comprising a plurality of cell pairs, each cell pair of the plurality of call pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory, and
control circuitry configured to apply a same pair of voltages to control gates of each cell pair of the plurality of cell pairs when checking for a match of the stored bit of data of the plurality of cell pairs and data value of the particular bit position of the pattern, wherein voltage levels of the same pair of voltages are responsive to the data value of the particular bit position of the pattern;
wherein the plurality of cell pairs comprises a first cell pair coupled to a first data line, a second cell pair coupled to a second data line, and a third cell pair coupled to a third data line.
2. The memory device of claim 1 , wherein the plurality of cell pairs further comprises additional cell pairs coupled to additional respective data lines.
3. The memory device of claim 1 , wherein the first cell pair is coupled in series with another cell pair of the plurality of cell pairs in a same string of memory cells.
4. The memory device of claim 1 , wherein the first cell pair is aligned in parallel with another cell pair of the plurality of cell pairs coupled to the first data line.
5. A method of operating a memory, comprising:
receiving a pattern of data to be programmed into a memory array of the memory; and
programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of the memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern;
wherein programming further comprises:
programming the first data state into a first memory cell of a particular cell pair of the plurality of cell pairs when a data value of a particular bit position of the pattern corresponding to the particular cell pair has a first value;
programming the second data state into the first memory cell of the particular cell pair when the data value of the particular bit position of the pattern has a second value;
programming the second data state into the second memory cell of the particular cell pair when the data value of the particular bit position of the pattern has the first value; and
programming the first data state into the second memory cell of the particular cell pair when the data value of the particular bit position has the second value.
6. The method of claim 5 , wherein each cell pair of the plurality of cell pairs are coupled in series in a same string of memory cells of the memory array.
7. The method of claim 5 , wherein each cell pair of the plurality of cell pairs are aligned in parallel along a same data line of the memory array.
8. A method of operating a memory, comprising:
receiving a pattern of data to be programmed into a memory array of the memory; and
programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of the memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern;
wherein cell pairs of the plurality of cell pairs are coupled to different data lines of the memory array.
9. The method of claim 8 , wherein each cell pair of the plurality of cell pairs are coupled to different respective data lines of the memory array.