Memory cells and memory arrays

1. A memory cell comprising:

first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions, the second transistor having third and fourth source/drain regions, and the third transistor having fifth and sixth source/drain regions; wherein the memory cell includes a pillar of semiconductor material extending through the second and third transistors, and which includes the third, fourth, fifth and sixth source/drain regions as well as channel regions of the second and third transistors;

a write wordline which includes a gate of the first transistor;

a first bitline under the second transistor and electrically coupled with the first source/drain region;

a second bitline above the third transistor and electrically coupled with the sixth source/drain region;

a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor;

wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor; and

wherein the channel region of the second transistor is longer than a channel region of the third transistor.

2. A memory cell, comprising:

first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions electrically coupled to one another through a first channel region, the second transistor having third and fourth source/drain regions electrically coupled to one another through a second channel region, the third transistor having fifth and sixth source/drain regions electrically coupled to one another through a third channel region; the fourth and fifth source/drain regions being electrically coupled to one another; the first, second and third transistors ascending upwardly relative to a semiconductor base in an order proceeding from the first transistor to the second transistor to the third transistor; the semiconductor base comprising monocrystalline semiconductor material;

a read bitline above the third transistor and electrically coupled with the sixth source/drain region;

a write bitline adjacent the first transistor and electrically coupled with the first source/drain region;

a write wordline which includes a gate of the first transistor;

a read wordline which includes a gate of the third transistor;

a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor; and

wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor.

3. An apparatus comprising a semiconductor base and a plurality of memory cells, each of the plurality of memory cells comprising:

a first transistor including first and second source/drain regions formed in the semiconductor base, a first channel region therebetween and a first gate controlling the first channel region, the first gate being electrically connected to a first wordline;

a second transistor including third and fourth source/drain regions, a second channel region therebetween and a second gate controlling the second channel region, the third and fourth source/drain regions and the second channel region being vertically disposed with one another between a first bit line and a common plate over the semiconductor base, and the second gate being electrically coupled to the second source/drain region of the first transistor;

wherein each of the plurality of memory cells further comprises a third transistor disposed above the second transistor, the third transistor including fifth and sixth source/drain regions vertically disposed with one another and a third channel region therebetween, the fifth source/drain region electrically coupled with the fourth source/drain region; and

wherein the second channel region is larger than the third channel region in length.