Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.
1. An apparatus comprising:
an integrated circuit memory device into which a plurality of memory cells, a logic unit and a write driver are incorporated,
wherein the logic unit is configured to perform a logic function on read data initially received from a first location of the plurality of memory cells and output result data responsive to the logic function, and
wherein the write driver is configured to receive the result data and to write the result data to the first location of the plurality of memory cells so that the result data replaces the read data initially received from the first location.
2. The apparatus of claim 1 , wherein the logic function comprises Boolean logic operations.
3. The apparatus of claim 1 , wherein the logic function comprises arithmetic operations.
4. The apparatus of claim 1 , wherein when the logic function comprises Boolean logic operations and arithmetic operations.
5. The apparatus of claim 1 , wherein the logic function comprises an AND operation.
6. The apparatus of claim 1 , wherein the logic function comprises an OR function.
7. The apparatus of claim 1 , wherein the logic function comprises a NOR operation.
8. The apparatus of claim 1 , wherein the logic function comprises an XOR operation.
9. The apparatus of claim 1 , wherein the logic function comprises a NAND operation.
10. An apparatus comprising:
a command decoder;
at least one bank of memory cells; and
a logic unit and a write driver,
wherein the command decoder, the at least one bank of memory cells, the logic unit and the write driver are incorporated into an integrated circuit memory device,
wherein the command decoder is configured to receive a first command accompanied by first data and, responsive to the first command, cause the logic unit to perform a logic function on the first data and second data that is initially received from a first location of the at least one bank of memory cells, the logic unit further caused to output result data responsive to the logic function, and
wherein the write driver is configured to receive the result data and to write the result data to the first location of the at least one bank of memory cells so that the result data replaces the second data initially received from the first location.
11. The apparatus of claim 10 , wherein the logic function comprises Boolean logic operations.
12. The apparatus of claim 10 , wherein the logic function comprises arithmetic operations.
13. The apparatus of claim 10 , wherein when the logic function comprises Boolean logic operations and arithmetic operations.
14. The apparatus of claim 10 , wherein the logic function comprises an AND operation.
15. The apparatus of claim 10 , wherein the logic function comprises an OR operation.
16. The apparatus of claim 10 , wherein the logic function comprises a NOR operation.
17. The apparatus of claim 10 , wherein the logic function comprises an XOR operation.
18. The apparatus of claim 10 , wherein the logic function comprises a NAND operation.
19. The apparatus of claim 10 , further comprising a select circuit,
wherein the select circuit is incorporated into the integrated circuit memory device, and
wherein the select circuit is configured to:
receive the result data,
receive write data to be written into the at least one bank of memory cells, and
route one of the result data and the write data to the write driver.
20. The apparatus of claim 19 , wherein the command decoder is further configured to, responsive to the first command, cause the select circuit to route the result data to the write driver.