Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.
1. In an integrated circuit memory device, a method of enhancing an ability of the memory device to interface with a parallel processor, the method performed within the integrated circuit memory device, the method comprising:
receiving, by a processing system within the memory device, an external command to perform an indivisible operation in the memory device;
responsive to the external command to perform the indivisible operation, reading, by the processing system within the memory device, data from a first location in at least one bank of memory cells within the memory device;
performing, by the processing system within the memory device, a logic function on the data read from the first location in the at least one bank of memory cells based, at least in part, on the command, wherein the processing system within the memory device generates results data;
writing, by the processing system within the memory device, the results data to the same first location in the at least one bank of memory cells from which the data was read; and
preventing, by the processing system within the memory device, access to the data read from the same first location in the at least one bank of memory cells while the data are being read, the processing function is being performed, and the results data are being written.
2. The method of claim 1 wherein the act of reading data from a first location comprises routing data from the first location to Boolean logic.
3. The method of claim 1 , wherein the act of performing, by a processing system within the memory device, a logic function on the data read from the at least one bank of memory cells comprises performing, by the processing system within the memory device, a Boolean logic function on the data read from the at least one bank of memory cells.
4. The method of claim 1 wherein the integrated circuit memory device further comprises a cache memory, and wherein the method further comprises:
reading, by the processing system within the memory device, data from the cache memory;
performing, by the processing system within the memory device, a function on the data read from the cache memory to generate results data; and
writing the results data to the cache memory.
5. The method of claim 1 , wherein said writing the results data is performed responsive, at least in part, to receipt of a precharge bit.
6. The method of claim 1 , wherein the indivisible operation is performed with a single access.
7. The method of claim 1 , wherein the external command is provided by a memory controller.
8. A method, comprising:
receiving, by a processing system within a memory device, a command to perform an atomic operation;
reading, by the processing system within the memory device, data from the memory device at an address responsive, at least in part, to receipt of the command;
performing, by the processing system within the memory device, a processing function on the data read from the address based, at least in part, on the atomic operation to generate results data; and
writing, by the processing system within the memory device, the results data to the same address.
9. The method of claim 8 , wherein the processing function comprises at least one of a logic function or an arithmetic operation.
10. The method of claim 8 , wherein the address comprises a cache memory address.
11. The method of claim 10 , wherein said performing a processing function comprises:
fetching a cache row based, at least in part, on a tag bit; and
transforming the data read to provide results data.
12. The method of claim 8 , wherein the processing function is performed as an indivisible whole with a single access.
13. The method of claim 8 , wherein the command is received via a network.
14. A method, comprising:
receiving a command at a processing unit of a memory device to perform an atomic operation;
receiving write data at the processing unit of the memory device;
reading, by the processing unit of the memory device, read data at an address in the memory device responsive, at least in part to receipt of the command;
performing, by the processing unit of the memory device, a Boolean operation on the read data and the write data to generate results data; and
writing, by the processing unit within a memory device, the results data to the same address.
15. The method of claim 14 , wherein the command is a cache reference command.
16. The method of claim 14 , wherein the command is provided by a memory controller coupled to the memory device.
17. The method of claim 14 , wherein said reading, said performing, and said writing are performed within the memory device in an indivisible manner responsive only to the command.
18. The method of claim 14 , wherein the command is received from a parallel processor.
19. The method of claim 14 , wherein said performing, by the processing unit of the memory, a Boolean operation on the read data and the write data to generate the results data is based, at least in part, on a precharge bit.