IP Library Granted Patent US 10,546,837
Granted Patent B2
US 10,546,837 · App. 16/006,746 · Granted Jan 28, 2020

Semiconductor device assemblies with lids including circuit elements

Inventor: Thomas H. Kinsley (Boise, ID)
Assignee: Micron Technology, Inc.
H01L25/0657H01L2225/06548H01L2225/06582H01L2225/06589
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Quick Facts
Patent No.
US 10,546,837
App. No.
16/006,746
Filed
Jun 12, 2018
Granted
Jan 28, 2020
Kind
B2
Art Unit
2898
USPC
257/690
Abstract

A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.

Claims (34)

1. A semiconductor device package, comprising:

a stack of semiconductor dies over a substrate;

the substrate including a plurality of electrical contacts;

an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies, the annular lower lid including a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening;

a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts; and

the upper lid disposed over the annular lower lid and the stack of semiconductor dies.

2. The semiconductor device package of claim 1 , wherein the lower lid comprises a metal.

3. The semiconductor device package of claim 1 , wherein the upper lid comprises a metal.

4. The semiconductor device package of claim 1 , wherein the circuit element is configured for wireless communication.

5. The semiconductor device package of claim 1 , wherein the circuit element is a sensor.

6. The semiconductor device package of claim 1 , wherein the circuit element is a first circuit element, and wherein the semiconductor device package includes a second circuit element disposed in the opening and electrically coupled to at least a second one of the plurality of electrical contacts.

7. The semiconductor device package of claim 1 , wherein the lower lid includes at least one via electrically coupling the circuit element to the first one of the plurality of electrical contacts.

8. The semiconductor device package of claim 7 , wherein the at least one via is electrically isolated from the lower lid.

9. The semiconductor device package of claim 7 , wherein the at least one via is electrically coupled to the first one of the plurality of electrical contacts by a solder joint.

10. A semiconductor device package, comprising:

a stack of semiconductor dies over a substrate;

the substrate including a plurality of electrical contacts;

a lid disposed over the substrate and surrounding the die stack, the lid including a lower surface coupled to the substrate, an upper surface above the stack of semiconductor dies, and an outer surface in which is formed an opening;

a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts.

11. The semiconductor device package of claim 10 , wherein the lid comprises a metal.

12. The semiconductor device package of claim 10 , wherein the circuit element is configured for wireless communication.

13. The semiconductor device package of claim 10 , wherein the circuit element is a sensor.

14. The semiconductor device package of claim 10 , wherein the circuit element is a first circuit element, and wherein the semiconductor device package includes a second circuit element disposed in the opening and electrically coupled to at least a second one of the plurality of electrical contacts.

15. The semiconductor device package of claim 10 , wherein the lid includes at least one via electrically coupling the circuit element to the first one of the plurality of electrical contacts.

16. The semiconductor device package of claim 15 , wherein the at least one via is electrically isolated from the lid.

17. The semiconductor device package of claim 15 , wherein the at least one via is electrically coupled to the first one of the plurality of electrical contacts by a solder joint.

18. The semiconductor device package of claim 10 , wherein the lid is a two-piece lid comprising an annular lower lid and an upper lid.

19. A semiconductor device assembly, comprising:

a semiconductor device package, including:

a stack of semiconductor dies over a substrate,

the substrate including a plurality of electrical contacts,

a lid disposed over the substrate and surrounding the die stack, the lid including a lower surface coupled to the substrate, an upper surface above the stack of semiconductor dies, and an outer surface in which is formed an opening, and

a first circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts; and

a second circuit element disposed outside of the semiconductor device package and configured to wirelessly communicate with the first circuit element.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2018
From: KINSLEY, THOMAS H.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046063/0626 →