Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures

1. An apparatus, comprising:

an output driver circuit configured to drive a channel based on a current channel state and a next channel state using a multi-level communication architecture, wherein the output driver circuit comprises a driver control logic circuit and a delay control logic circuit each configured to receive the current channel state and the next channel state in parallel, wherein the driver control logic circuit is configured to, based on the next channel state, determine a first driver control value of a first driver control signal that causes the output driver circuit to drive a first signal line of the channel from a first value associated with the current channel state to a second value associated with the next channel state and determine a second driver control value of a second driver control signal that causes the output driver circuit to drive a second signal line of the channel from a third value associated with the current channel state to a fourth value associated with the next channel state, wherein the current channel state includes to a first respective collective value that corresponds to at least the first value on the first signal line and the third value on the second signal line and the current channel state includes a respective collective value that corresponds to at least the second value on the first signal line and the fourth value on the second signal line, wherein, in parallel with determination of the first driver control value of the first driver control signal and the second driver control value of the second driver control signal by the driver control logic circuit, the delay control logic circuit is configured to, based on a comparison of the current channel state and the next channel state, determine a first offset delay to apply to the first driver control signal to cause the output driver circuit to delay transition of the first signal line of the channel from the first value to the second value by the first offset delay and to determine a second offset delay to apply to the second driver control signal to cause the output driver circuit to delay transition of the second signal line of the channel from the third value to the fourth value by the second offset delay, wherein the output driver circuit is configured to drive the first signal line to the second value in response to the first driver control signal having the first driver control value after applying the first offset delay and to drive the second signal line to the fourth value in response to the first driver control signal having the first driver control value after applying the second offset delay, wherein the first offset delay is different than the second offset delay.

2. The apparatus of claim 1 , wherein the delay control logic is configured to select the first offset delay from a lookup table.

3. The apparatus of claim 1 , wherein the output driver circuit is configured to determine the first offset delay and the second offset delay based on a channel state associated with a combination of the first and second signal lines.

4. The apparatus of claim 1 , wherein the output driver circuit is configured to select the first offset delay and select the second offset delay based on a comparison between a current channel state associated with a combination of the first and second signal lines and a next channel state associated with a combination of the first and second signal lines.

5. The apparatus of claim 1 , wherein the multi-level communication architecture is a differential architecture, and wherein the channel includes a plurality of signal lines, wherein a receiver circuit is configured to provide the output signal having a value that is based on a comparison of two signal lines of the plurality of signal lines.

6. An apparatus, comprising:

an output driver circuit configured to drive a channel based on a current channel state and a next channel state using a multi-level communication architecture, wherein a channel includes a plurality of signal lines and the current channel state and the next channel state represents a respective collective value of the signals on the plurality of signal lines, wherein the output driver circuit comprises a driver control logic circuit and a delay control logic circuit each configured to receive the current channel state and the next channel state in parallel, wherein the delay control logic circuit is configured to determine a respective offset delay to apply to transition of each of the plurality of signal lines based on a comparison of the current channel state with the next channel state of the channel and, in parallel with the determination of the respective offset delay to apply to transition of each of the plurality of signal lines by delay control logic circuit, the driver control logic circuit is configured to determine a respective logic level value to drive on each of the plurality of signal lines based on the next channel state.

7. The apparatus of claim 6 , wherein, based on the comparison between the previous channel state with the current channel state, the output driver circuit is configured to apply a first offset delay to delay transition of a first signal line of the plurality of signal lines to a first logic level value determined by the driver control logic circuit and to apply a second offset delay to delay transition of a second signal line of the plurality of signal lines to a second logic level value determined by the driver control logic circuit.

8. The apparatus of claim 7 , wherein the output circuit comprises a delay circuit having a plurality of delays, wherein the delay circuit is configured to couple a first control signal from the driver control logic to a first delay of the plurality of delays based on the first offset delay and configured to couple a second control signal from the driver control logic to a second delay of the plurality of delays based on the second offset delay, wherein the first control signal controls transition of the first signal line to a first logic level value determined by the driver control logic circuit and the second control signal controls transition of the second signal line to the first logic level value determined by the driver control logic circuit.

9. The apparatus of claim 6 , further comprising a receiver circuit is configured to determine an input signal based on a comparison of two signal lines of the plurality of signal lines.

10. The apparatus of claim 6 , wherein the multi-level communication architecture includes mobile industry processor interface (MIPI) C-PHY architecture.

11. The apparatus of claim 6 , wherein the multi-level communication architecture includes pulse-amplitude modulation.

12. The apparatus of claim 6 , wherein each of the plurality of signal lines may be set to one of three different voltages.

13. The apparatus of claim 6 , wherein the delay control logic circuit is configured to select the first offset delay and the second offset delay from a lookup table based on the comparison between the next channel state and the current channel state.

14. A method, comprising:

comparing the current channel state with the next channel state of a channel having a plurality of signal lines;

based on the comparison:

selecting a first control signal value of a first control signal to drive a first next logic level value on a first signal line of the plurality of signal lines and selecting a first offset delay to apply to the first control signal to control timing of transition of the first signal line of the plurality of signal lines from a first current logic level value associated with the current channel state to the first next logic level value associated with the next channel state; and

selecting a second control signal value of a second control signal to drive a second next logic level value on a second signal line of the plurality of signal lines based on the next channel state and selecting a second offset delay to apply to the second control signal to control timing of transition of the second signal line of the plurality of signal lines from a second current logic level value associated with the current channel state to the second next logic level value associated with the next channel state.

15. The method of claim 14 , further comprising:

driving the first signal line to the first next logic level value associated with the next channel state responsive to the first control signal; and

driving the second signal line to the second next logic level value associated with the next channel state responsive to the second control signal.

16. The method of claim 14 , further comprising selecting a delay circuit of a plurality of delay circuits, wherein the selected delay circuit is configured to apply the first offset delay to the first control signal.

17. The method of claim 14 , wherein the first offset delay is different than the second offset delay.