Methods for parity error alert timing interlock and memory devices and systems employing the same
Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.
1. A method for operating a memory device comprising:
detecting a parity error associated with a command or address signal;
enabling a parity error alert signal in response to detecting the parity error;
detecting that a period of time substantially equal to a parity error alert pulse width value has elapsed;
in response to detecting that the period of time has elapsed, detecting if memory operations are in progress, wherein the memory operations were initiated before detecting the parity error; and
disabling the parity error alert signal in response to detecting that no memory operations are in progress.
2. The method of claim 1 , wherein detecting that the period of time has elapsed further comprises detecting that a timer has counted the period of time.
3. The method of claim 2 , wherein the timer is at least one of an analog delay element or a digital counter.
4. The method of claim 1 , wherein the parity error alert pulse width value is substantially equal to 90 ns.
5. The method of claim 1 , wherein detecting if the memory operations are in progress further comprises:
latching a precharge timer clock in response to detecting that a command in-progress signal is enabled, wherein the precharge timer clock synchronizes a precharge operation of a memory of the memory device;
unlatching the precharge timer clock in response to detecting that the command in-progress signal is disabled;
generating a precharge pulse in response to detecting that the command in-progress signal is disabled and the precharge timer clock is deasserted; and
determining that no memory operations are in progress based on detecting the generated precharge pulse.
6. The method of claim 2 , wherein detecting that the timer has counted the period of time further comprises:
receiving the parity error alert pulse width value;
loading the timer with the received parity error alert pulse width value;
starting the timer in response to enabling the parity error alert signal; and
setting a signal indicating that the timer has counted the period of time substantially equal to the received parity error alert pulse width value.
7. The method of claim 6 , wherein receiving the parity error alert pulse width value further comprises:
receiving a minimum allowed parity error alert pulse width value;
receiving a tolerance margin value for the minimum allowed parity error alert pulse width; and
generating the parity error alert pulse width value based on the received minimum allowed parity error alert pulse width value and the received tolerance margin value.
8. The method of claim 1 , wherein the memory device is a DRAM device.
9. A memory device, comprising:
a parity error detector configured to receive a command or address signal and generate a parity error signal;
a timer coupled to the parity error detector configured with a parity error alert pulse width value and further configured to receive the parity error signal and generate a timeout signal;
an internal operations in progress detector configured to determine if internal memory operations are in progress and generate an internal operations done signal when no internal memory operations are in progress, wherein the internal memory operations were initiated before the parity error detector generates the parity error signal; and
a parity error alert signal generator coupled to the internal operations in progress detector, the timer, and the parity error detector, configured to generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal.
10. The memory device of claim 9 , wherein the parity error detector is further configured to determine a parity of the command or address signal, compare the determined parity with a parity scheme of the memory device, and drive the parity error signal to a logic one value in response to detecting that the determined parity violates the parity scheme of the memory device.
11. The memory device of claim 9 , wherein the timer is at least one of an analog delay element or a digital counter.
12. The memory device of claim 9 , wherein the parity error alert pulse width value is programmable.
13. The memory device of claim 9 , wherein the parity error alert pulse width value is substantially equal to 90 ns.
14. The memory device of claim 9 , wherein the internal operations in progress detector further comprises:
a precharge generator configured to receive a command in-progress signal and a precharge timer clock;
sequential logic configured to latch the precharge timer clock in response to detecting that the command in-progress signal is asserted; and
combinational logic configured to generate a precharge pulse in response to detecting that the command in-progress signal is deasserted and the precharge timer clock is deasserted, wherein the internal operations done signal is generated in response to the generation of the precharge pulse.
15. The memory device of claim 14 , wherein the asserted command in-progress signal corresponds to a logic zero value, the deasserted command in-progress signal corresponds to a logic one value, the deasserted precharge timer clock corresponds to the logic zero value, and the precharge timer clock synchronizes a precharge operation of a memory of the memory device.
16. The memory device of claim 10 , wherein the timer is further configured to start a timer operation in response to detecting a state transition of the parity error signal from a logic zero value to the logic one value, and further configured to activate the timeout signal in response to detecting that a period substantially equal to the configured parity error alert pulse width value has elapsed since the start of the timer operation.
17. The memory device of claim 10 , wherein the parity error alert signal generator further comprises logic circuitry configured to assert the parity error alert signal in response to detecting a state transition of the parity error signal from a logic zero value to the logic one value, and deassert the parity error alert signal in response to detecting the timeout signal and the internal operations done signal.
18. The memory device of claim 17 , wherein the logic circuitry further comprises logic configured to deassert the parity error alert signal if the timeout signal is the logic one value and the internal operations done signal is the logic one value.
19. The memory device of claim 17 , wherein the parity error alert signal generator asserts the parity error alert signal by driving the parity error alert signal to the logic zero value, and deasserts the parity error alert signal by driving the parity error alert signal to the logic one value.
20. A memory device, comprising:
means for detecting a parity error in a command or address signal;
means for counting a period of time substantially equal to a parity error alert pulse width value;
means for detecting whether one or more internal memory operations are in progress; and
means for generating a parity error alert signal in response to detecting the parity error, counting the period of time, and detecting whether the one or more internal memory operations are in progress, wherein the parity error alert signal is asserted in response to detecting the parity error, and the parity error alert signal is deasserted in response to counting the period of time and detecting no internal memory operations in progress, and wherein the one or more internal memory operations were initiated before detecting the parity error.