Managing write operations during a power loss
View Patent ↗Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
1. A computer-implemented method, comprising:
detecting that an asynchronous power loss event (“APL”) has occurred;
determining that a write operation to a first type of non-volatile memory element is in progress, wherein the write operation includes a first physical address and a data, and wherein the first physical address corresponds to a logical address;
canceling the write operation in response to determining that the write operation is to the first type of non-volatile memory element;
retrieving the data from a volatile memory element associated with the non-volatile memory element of the first type;
sending a request for a second physical address, wherein the request includes the first physical address and wherein the request designates a second type of non-volatile memory element;
receiving the second physical address corresponding to the logical address, wherein the second physical address points to the second type of non-volatile memory element; and
storing the data at the second physical address in the non-volatile memory element of the second type.
2. The method of claim 1 , further comprising:
determining, in response to the APL, that a second write operation is in progress;
determining that the second write operation is to the second type of non-volatile memory element; and
allowing the second write operation to complete.
3. The method of claim 1 , further comprising:
determining, in response to the APL, that a second write operation to the first type of non-volatile memory element is in progress;
comparing a value of a timer associated with the second write operation to an expected write operation duration value, wherein the expected write operation duration value is associated with the first type of non-volatile memory element; and
allowing, based on the comparing, the second write operation to complete.
4. The method of claim 1 , wherein a write speed of the first type of non-volatile memory element is slower than a write speed of the second type of non-volatile memory element.
5. The method of claim 1 , wherein a storage density of the first type of non-volatile memory element is greater than a storage density of the second type of non-volatile memory element.
6. The method of claim 1 , further comprising:
storing the data in a buffer, wherein the buffer is made available for canceled write operations in response to a global interrupt.
7. The method of claim 1 , further comprising:
determining, based on the first type of non-volatile memory element, an encoding scheme; and
decoding, based on the encoding scheme, the data before storing the data at the second physical address.
8. A non-transitory computer-readable medium storing instructions, which when executed by a processing device, cause the processing device to perform a method comprising:
detecting that an asynchronous power loss event (“APL”) has occurred;
determining that a write operation to a first type of non-volatile memory element is in progress, wherein the write operation includes a first physical address and a data, and wherein the first physical address corresponds to a logical address;
canceling the write operation in response to determining that the write operation is to the first type of non-volatile memory element;
retrieving the data from a volatile memory element associated with the non-volatile memory element of the first type;
sending a request for a second physical address, wherein the request includes the first physical address and wherein the request designates a second type of non-volatile memory element;
receiving the second physical address corresponding to the logical address, wherein the second physical address points to the second type of non-volatile memory element; and
storing the data at the second physical address in the non-volatile memory element of the second type.
9. The non-transitory computer-readable medium of claim 8 , the method further comprising:
determining, in response to the APL, that a second write operation is in progress;
determining that the second write operation is to the second type of non-volatile memory element; and
allowing the second write operation to complete.
10. The non-transitory computer-readable medium of claim 8 , the method further comprising:
determining, in response to the APL, that a second write operation to the first type of non-volatile memory element is in progress;
comparing a value of a timer associated with the second write operation to an expected write operation duration value, wherein the expected write operation duration value is associated with the first type of non-volatile memory element; and
allowing, based on the comparing, the second write operation to complete.
11. The non-transitory computer-readable medium of claim 8 , wherein a write speed of the first type of non-volatile memory element is slower than a write speed of the second type of non-volatile memory element.
12. The non-transitory computer-readable medium of claim 8 , wherein a storage density of the first type of non-volatile memory element is greater than a storage density of the second type of non-volatile memory element.
13. The non-transitory computer-readable medium of claim 8 , the method further comprising:
storing the data in a buffer, wherein the buffer is made available for canceled write operations in response to a global interrupt.
14. The non-transitory computer-readable medium of claim 8 , the method further comprising:
determining, based on the first type of non-volatile memory element, an encoding scheme; and
decoding, based on the encoding scheme, the data before storing the data at the second physical address.
15. A system comprising:
a volatile memory element;
a first type of non-volatile memory element;
a second type of non-volatile memory element; and
a processing device coupled to the volatile memory element, the first type of non-volatile memory element, and the second type of non-volatile memory element, the processing device configured to:
detect that an asynchronous power loss event (“APL”) has occurred;
determine that a write operation to the first type of non-volatile memory element is in progress, wherein the write operation includes a first physical address and a data, and wherein the first physical address corresponds to a logical address;
cancel the write operation in response to determining that the write operation is to the first type of non-volatile memory element;
retrieve the data from the volatile memory element associated with the non-volatile memory element of the first type;
send a request for a second physical address, wherein the request includes the first physical address and wherein the request designates the second type of non-volatile memory element;
receive the second physical address corresponding to the logical address, wherein the second physical address points to the second type of non-volatile memory element; and
store the data at the second physical address in the non-volatile memory element of the second type.
16. The system of claim 15 , the processing device further configured to:
determine, in response to the APL, that a second write operation is in progress;
determine that the second write operation is to the second type of non-volatile memory element; and
allow the second write operation to complete.
17. The system of claim 15 , the processing device further configured to:
determine, in response to the APL, that a second write operation to the first type of non-volatile memory element is in progress;
compare a value of a timer associated with the second write operation to an expected write operation duration value, wherein the expected write operation duration value is associated with the first type of non-volatile memory element; and
allow, based on the comparing, the second write operation to complete.
18. The system of claim 15 , wherein a write speed of the first type of non-volatile memory element is slower than a write speed of the second type of non-volatile memory element.
19. The system of claim 15 , the processing device further configured to:
store the data in a buffer, wherein the buffer is made available for canceled write operations in response to a global interrupt.
20. The system of claim 15 , the processing device further configured to:
determine, based on the first type of non-volatile memory element, an encoding scheme; and
decode, based on the encoding scheme, the data before storing the data at the second physical address.