Host side caching security for flash memory

1. A memory system comprising:

a memory array;

a controller, wherein the controller is programmed to perform operations comprising:

receiving a read request from a host device, the read request indicating a first logical address;

determining a first physical location at the memory array associated with the first logical address;

reading a first data unit from the first physical location;

accessing a first secured logical-to-physical (L2P) pointer, the first secured L2P pointer indicating a first encrypted physical address for the first physical location and the first logical address corresponding to a first clear physical address for the first physical location; and

sending the first data unit and the first secured L2P pointer to the host device, the first secured L2P pointer for storage at a host memory.

2. The memory system of claim 1 , wherein accessing the first secured L2P pointer comprises reading a first L2P pointer from an L2P table stored at the memory array, the first L2P pointer indicating the first logical address and the first clear physical address for the first physical location at the memory array associated with the first logical address.

3. The memory system of claim 1 , wherein the controller is further programmed to perform operations comprising:

generating a secured L2P table comprising a number of secured L2P pointers comprising the first secured L2P pointer and a second secured L2P pointer; and

storing the secured L2P table at the memory array.

4. The memory system of claim 3 , wherein the controller is further programmed to perform operations comprising:

receiving from the host device a second read request comprising a second logical address;

accessing, from the secured L2P table stored at the memory array, a second secured L2P pointer indicating the second logical address and a second encrypted physical address for a second physical location at the memory array;

generating a second clear physical address for the second physical location using the second encrypted physical address;

reading a second data unit from the second physical location of the memory system using the second clear physical address; and

sending the second data unit to the host device.

5. The memory system of claim 1 , wherein the controller is further programmed to perform operations comprising:

receiving a request from the host device, the request indicating a second logical address;

accessing a second secured L2P pointer, the second secured L2P pointer indicating the second logical address and a second encrypted physical address for a second physical location at the memory array; and

sending the second secured L2P pointer to the host device.

6. The memory system of claim 1 , wherein the controller is further programmed to perform operations comprising:

receiving a second read request from the host device, wherein the second read request comprises an indication of the first encrypted physical address;

generating the first clear physical address for the first physical location using the first encrypted physical address;

reading a second data unit from the first physical location; and

returning the second data unit to the host device.

7. The memory system of claim 1 , wherein the controller is further programmed to perform operations comprising:

receiving, from the host device, a request for a set of L2P pointers, the set of L2P pointers including the first L2P pointer; and

sending, to the host device, a set of secured L2P pointers including the first secured L2P pointer, wherein the first secured L2P pointer corresponds to the first L2P pointer.

8. The memory system of claim 7 , wherein the controller is further programmed to perform operations comprising reading the set of secured L2P pointers from the memory array.

9. A method comprising:

receiving, by a memory system, a read request from a host device, the read request indicating a first logical address;

determining, by the memory system, a first physical location at a memory array associated with the first logical address;

reading, by the memory system, a first data unit from the first physical location;

accessing, by the memory system, a first secured logical-to-physical (L2P) pointer indicating a first encrypted physical address for the first physical location and the first logical address corresponding to a first clear physical address for the first physical location; and

sending, by the memory system, first data unit and the first secured L2P pointer to the host device, the first secured L2P pointer for storage at a host memory.

10. The method of claim 9 , wherein accessing the first secured L2P pointer comprises reading, from an L2P table stored at the memory system, a first L2P pointer, the first L2P pointer indicating the first logical address and the first clear physical address at the memory system associated with the first logical address.

11. The method of claim 9 , further comprising:

generating a secured L2P table comprising a number of secured L2P pointers comprising the first secured L2P pointer and a second secured L2P pointer; and

storing the secured L2P table at the memory system.

12. The method of claim 11 , further comprising:

receiving from the host device a second read request comprising a second logical address;

accessing, from the secured L2P table stored at the memory system, a second secured L2P pointer indicating the second logical address and a second encrypted physical address;

generating a second clear physical address for a second physical location at the memory array using the second encrypted physical address;

reading a second data unit from the second physical location using the second clear physical address; and

sending the second data unit to the host device.

13. The method of claim 9 , further comprising:

receiving a request from the host device, the request indicating a second logical address;

accessing a second secured L2P pointer, the second secured L2P pointer indicating the second logical address and a second encrypted physical address for a second physical location at the memory array; and

sending the second secured L2P pointer to the host device.

14. The method of claim 9 , further comprising:

receiving a second read request from the host device, wherein the read request comprises an indication of the first encrypted physical address;

generating the first clear physical address for the first physical location using the first encrypted physical address;

reading a second data unit from the first physical location; and

returning the second data unit to the host device.

15. The method of claim 9 , further comprising:

receiving, from the host device, a request for a set of L2P pointers, the set of L2P pointers including the a first L2P pointer; and

sending, to the host device, a set of secured L2P pointers including the first secured L2P pointer, wherein the first secured L2P pointer corresponds to the first L2P pointer.

16. The method of claim 15 , further comprising reading the set of secured L2P pointers from the memory system.

17. A non-transitory computer readable medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising:

receiving a read request from a host device, the read request indicating a first logical address;

determining a first physical location at a memory array associated with the first logical address;

reading a first data unit from the first physical location;

accessing a first secured logical-to-physical (L2P) pointer indicating a first logical address associated with a first clear physical address for the first physical location and a first encrypted physical address for the first physical location; and

sending the first secured L2P pointer to a host device for storage at a host memory.

18. The non-transitory computer readable medium of claim 17 , wherein accessing the first secured L2P pointer comprises reading, from an L2P table stored at a memory system, a first L2P pointer, the first L2P pointer indicating the first logical address and the first clear physical address at the memory system associated with the first logical address.

19. The non-transitory computer readable medium of claim 17 , further comprising instructions thereon that, when executed by a processor, cause the processor to further perform operations comprising:

storing a secured L2P table at a memory system, the secured L2P table comprising the first secured L2P pointer.

20. The non-transitory computer readable medium of claim 19 , further comprising instructions thereon that, when executed by a processor, cause the processor to further perform operations comprising:

receiving from the host device a second read request comprising a second logical address;

accessing, from the secured L2P table stored at a memory system, a second secured L2P pointer indicating the second logical address and a second encrypted physical address;

generating a second clear physical address for a second physical location at the memory array using the second encrypted physical address;

reading a second data unit from the second physical location using the second clear physical address; and

sending the second data unit to the host device.