3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
1. A semiconductor device, comprising:
a first die including:
a first top surface and a first bottom surface,
a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a top portion extending past the first top surface and a bottom portion extending past the first bottom surface, and
a first substantially helical conductor disposed around the TSV;
a second die including:
a second top surface having an opening in which the bottom portion of the TSV is disposed, and
a second substantially helical conductor disposed around the opening in the second top surface; and
a third die including:
a second bottom surface having an opening in which the top portion of the TSV is disposed, and
a third substantially helical conductor disposed around the opening in the second bottom surface.
2. The semiconductor device of claim 1 , wherein the first substantially helical conductor is configured to induce a change in a magnetic field in the TSV in response to a first changing current in the first substantially helical conductor,
wherein the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the bottom portion of the TSV, and
wherein the third substantially helical conductor is configured to have a third changing current induced therein in response to the change in the magnetic field in the top portion of the TSV.
3. The semiconductor device of claim 1 , wherein the TSV comprises a ferromagnetic or a ferrimagnetic material.
4. The semiconductor device of claim 1 , wherein the first substantially helical conductor comprises a different number of turns around the TSV than at least one of the second and third substantially helical conductors.
5. The semiconductor device of claim 1 , wherein the first, second and third substantially helical conductors comprise a same number of turns around the TSV.
6. The semiconductor device of claim 1 , wherein the first, second and third substantially helical conductors are coaxially aligned with the TSV.
7. The semiconductor device of claim 1 , wherein the first substantially helical conductor comprises more than one turn around the TSV, and at least one of the second and third substantially helical conductors comprises more than one turn around the TSV.
8. The semiconductor device of claim 1 , wherein the first, second and third substantially helical conductors are electrically isolated from each other and from the TSV.
9. The semiconductor device of claim 1 , wherein one of the first, second and third substantially helical conductors is electrically connected to a power supply and another of the first, second and third substantially helical conductors is electrically connected to a load.