3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
1. A semiconductor device, comprising:
a first die including:
a first surface,
a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface, and
a first substantially helical conductor disposed around the TSV; and
a second die including:
a second surface,
an opening in the second surface in which the portion of the TSV is disposed, and
a second substantially helical conductor disposed around the opening.
2. The semiconductor device of claim 1 , wherein the first substantially helical conductor is configured to induce a change in a magnetic field in the TSV in response to a first changing current in the first substantially helical conductor, and wherein the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the portion of TSV.
3. The semiconductor device of claim 1 , wherein the first die further includes:
a second TSV extending at least substantially through the first die, the second TSV having a portion extending past the first surface, and
a third substantially helical conductor disposed around the second TSV, and
wherein the second die further includes:
a second opening in the second surface in which the portion of the second TSV is disposed, and
a fourth substantially helical conductor disposed around the second opening.
4. The semiconductor device of claim 1 , wherein the TSV comprises a ferromagnetic or a ferrimagnetic material.
5. The semiconductor device of claim 1 , wherein the first substantially helical conductor comprises a different number of turns around the TSV than the second substantially helical conductor.
6. The semiconductor device of claim 1 , wherein the first and second substantially helical conductors comprise a same number of turns around the TSV.
7. The semiconductor device of claim 1 , wherein the first and second substantially helical conductors are coaxially aligned with the TSV.
8. The semiconductor device of claim 1 , wherein the first substantially helical conductor comprises more than one turn around the TSV, and the second substantially helical conductor comprises more than one turn around the TSV.
9. The semiconductor device of claim 1 , wherein the first substantially helical conductor and the second substantially helical conductor are electrically isolated from each other and from the TSV.
10. The semiconductor device of claim 1 , wherein one of the first and second substantially helical conductors is electrically connected to a power supply and another of the first and second substantially helical conductors is electrically connected to a load.
11. The semiconductor device of claim 1 , wherein the first surface is a lower surface of a substrate material of the first die.
12. The semiconductor device of claim 1 , wherein the first surface is an upper surface of the first die on an opposite side of the first substantially helical conductor from a substrate material of the first die.