IP Library Granted Patent US 11,003,537
Granted Patent B2
US 11,003,537 · App. 15/991,463 · Granted May 11, 2021

Determining validity of data read from memory by a controller

Inventors: Alberto Troia (Munich, DE); Antonino Mondello (Messina, IT)
Assignee: Micron Technology, Inc.
G06F11/1417G06F11/073G06N3/04H04L9/3239
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Quick Facts
Patent No.
US 11,003,537
App. No.
15/991,463
Filed
May 29, 2018
Granted
May 11, 2021
Kind
B2
Art Unit
2186
USPC
713/2
Abstract

A method includes: generating, based on a hash function using at least one input including first data, a first digest; storing the first data in a memory; reading the first data from the memory; generating, based on the read data, a second digest; comparing the first digest and the second digest; and determining, based on comparing the first digest and the second digest, whether the read data is corrupted.

Claims (54)

1. A method comprising:

generating, based on a hash function using at least one input including first data, a first digest;

storing the first data in a memory, the first data including matrices of an artificial neural network;

reading the first data from the memory;

generating, based on the read data, a second digest;

comparing the first digest and the second digest; and

determining, based on comparing the first digest and the second digest, whether the read data is corrupted.

2. The method of claim 1 , wherein the at least one input used by the hash function further includes at least one of:

an address at which the first data is stored in the memory; or

metadata associated with the first data.

3. The method of claim 1 , wherein the memory is a boot device of a controller, the method further comprising copying the read data and the first digest to a system memory of the controller.

4. The method of claim 1 , wherein reading the first data from the memory comprises reading the first data by a first computing device, the method further comprising sending the read data to a second computing device, wherein comparing the first digest and the second digest is performed by the second computing device.

5. The method of claim 1 , further comprising, in response to determining that the read data is corrupted, performing at least one action.

6. The method of claim 5 , wherein the first data is stored in the memory by a controller, and the at least one action comprises at least one of:

sending a signal to the controller that indicates the first data is corrupted;

re-reading the first data from the memory;

terminating a process executing on the controller; or

containing data identified as being corrupted.

7. The method of claim 1 , wherein the memory is a boot device, the method further comprising copying, by a controller, a plurality of rows of data from the boot device to a system memory of the controller, wherein the rows include a first row and a second row, the first data is stored in the first row, and comparing the first digest and the second digest is performed prior to copying the second row.

8. The method of claim 1 , wherein the memory is a code area of a system memory of a first computing device, the method further comprising copying a plurality of rows of data from the code area to a runtime area of the system memory, wherein the rows include a first row and a second row, the first data is stored in the first row, and comparing the first digest and the second digest is performed prior to copying the second row.

9. The method of claim 8 , further comprising sending the first digest to a second computing device, wherein generating the second digest is performed by the second computing device.

10. The method of claim 9 , wherein the first computing device is a field-programmable gate array (FPGA), and the second computing device is a FPGA, a controller, or a computing device executing a hypervisor.

11. The method of claim 1 , further comprising:

storing the first digest in the memory as being associated with the stored first data;

generating a third digest for a block of data stored in the memory, wherein the block of data includes a plurality of rows of data, and the rows include a first row storing the first data; and

determining, using the third digest, whether the block of data is corrupted.

12. The method of claim 1 , wherein storing the first data comprises writing, by a controller, the first data to a volatile memory or a non-volatile memory.

13. The method of claim 1 , wherein the first data is stored in a first row of a plurality of rows stored in the memory, and the plurality of rows corresponds to the matrices of the artificial neural network.

14. The method of claim 1 , wherein storing the first data comprises writing the first data by a controller, the method further comprising, after reading the first data, storing the read data in a system memory of the controller.

15. The method of claim 1 , wherein storing the first data comprises writing the first data by a controller, and the memory is a system memory of the controller.

16. The method of claim 1 , wherein storing the first data comprises storing the first data by a first computing device, the method further comprising sending the first digest to a second computing device, wherein comparing the first digest and the second digest is performed by the second computing device.

17. The method of claim 1 , wherein storing the first data comprises storing the first data in a first row of a plurality of rows stored in the memory, the method further comprising generating a third digest for a block of data stored in the memory, wherein the block includes the plurality of rows, and wherein the third digest is generated using the hash function with at least one input including at least one of:

data stored in the plurality of rows; or

a plurality of respective digests, wherein each respective digest corresponds to a digest generated for a respective row of the plurality of rows.

18. A system comprising:

at least one processor; and

memory containing instructions configured to instruct the at least one processor to:

generate, based on a hash function using data as an input, a first digest;

store the data in a first memory, the data including matrices of an artificial neural network;

read the data from the first memory;

generate, based on the read data, a second digest; and

determine, based on a comparison of the first digest and the second digest, whether the read data is corrupted.

19. The system of claim 18 , wherein:

the first memory comprises a system memory, or a memory of a boot device;

the at least one processor comprises a controller, a field-programmable gate array, or a computing device executing a hypervisor; and

the method further comprises storing the first digest in at least one of the first memory or a second memory.

20. A non-transitory computer storage medium storing instructions which, when executed by at least one processor of a vehicle, cause the at least one processor to:

collect sensor data from at least one sensor of the vehicle;

generate a first digest using a hash function, wherein the hash function uses inputs including a page of data, and a first address at which the page is to be stored after generating the first digest;

store the page at the first address in a memory, the page including at least a portion of an artificial neural network;

read the page from the first address of the memory;

generate, based on the read page and the first address, a second digest;

determine, based on a comparison of the first digest and the second digest, whether the read page is corrupted;

in response to determining that the read page is not corrupted, generating an operating instruction for the vehicle from the artificial neural network using the sensor data as an input to the artificial neural network.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: MONDELLO, ANTONINO; TROIA, ALBERTO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047140/0986 →
Continuity (1)
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