Output driver for multi-level signaling
View Patent ↗A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.
1. An electronic memory apparatus, comprising:
an array of memory cells;
a controller coupled with the array of memory cells; and
a driver coupled with the controller and configured to generate a multi-level signal modulated using a first modulation scheme having at least three levels related to the array of memory cells, the driver including a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity.
2. The apparatus of claim 1 , wherein:
the first switching component and the second switching component are configured to generate a linear output current relative to an output voltage of the first switching component and the second switching component.
3. The apparatus of claim 1 , wherein:
the first switching component comprises a pmos transistor and the second switching component comprises an nmos transistor.
4. The apparatus of claim 1 , wherein:
the first switching component and the second switching component are coupled with a common voltage source and an output node of the driver in parallel.
5. The apparatus of claim 1 , wherein the driver further comprises:
a pull-down circuit including a third switching component having the first gate polarity and a fourth switching component having the second gate polarity.
6. The apparatus of claim 5 , wherein:
the third switching component comprises a pmos transistor and the fourth switching component comprises an nmos transistor.
7. The apparatus of claim 5 , wherein:
the third switching component and the fourth switching component are coupled with a common ground node and an output node of the driver in parallel.
8. The apparatus of claim 5 , wherein:
a gate of the first switching component of the pull-up circuit is coupled with a gate of the fourth switching component of the pull-down circuit.
9. The apparatus of claim 5 , wherein:
a gate of the second switching component of the pull-up circuit is coupled with a gate of the third switching component of the pull-down circuit.
10. The apparatus of claim 1 , wherein:
the multi-level signal is encoded with information using a pulse-amplitude modulation (PAM) scheme.