Transistors comprising a pair of source/drain regions having a channel there-between
View Patent ↗A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si 1-y Ge y , where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si 1-x Ge x , where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.
1. A transistor comprising:
a pair of source/drain regions having a channel there-between;
a transistor gate construction operatively proximate the channel;
the channel comprising Si 1-y Ge y , where “y” is from 0 to 0.6; and
at least a portion of each of the source/drain regions comprising Si 1-x Ge x , where “x” is from 0.5 to 1, neither of the portions nor the Si 1-x Ge x therein is directly against the channel, each of the source/drain regions comprises the Si 1-y Ge y and which is directly against the Si 1-y Ge y of the channel, “y” being greater than 0.
2. The transistor of claim 1 wherein each of the source/drain regions comprises at least a part thereof comprising a conductivity-increasing dopant therein that is of maximum concentration of said conductivity-increasing dopant within the respective source/drain region, each of the portions being within said part.
3. The transistor of claim 1 wherein the channel comprises a conductivity-increasing dopant therein that is at a maximum concentration in the channel of no greater than 1×10 14 atoms/cm 3 .
4. The transistor of claim 1 wherein the channel comprises no measurable quantity of conductivity-increasing dopant therein.
5. The transistor of claim 1 being elevationally-extending.
6. The transistor of claim 5 wherein one of the pair of source/drain regions is directly above the other of the pair of source drain regions.
7. The transistor of claim 5 being vertical or within 10° of vertical.
8. The transistor of claim 7 wherein the pair of source/drain regions and the channel in combination have an aspect ratio of at least 3:1.
9. The transistor of claim 1 being a thin-film transistor.
10. The transistor of claim 1 wherein “x” is greater than “y”.
11. The transistor of claim 1 wherein “x” equals “y”.
12. A transistor comprising:
a pair of solid source/drain regions having a channel there-between;
a transistor gate construction operatively proximate the channel;
the channel comprising a direction of current flow there-through between the pair of solid source/drain regions; and
a pair of insulator-material regions in the channel that are each elongated orthogonal to the current-flow direction, are each extending completely through the channel orthogonal to the current-flow direction, and are each no thicker than 10 Angstroms in the current-flow direction, the insulator-material regions individually being directly against one of the pair of solid source/drain regions.
13. The transistor of claim 12 wherein each of the insulator-material regions is at least 2 Angstroms thick.
14. The transistor of claim 13 wherein each of the insulator-material regions is no more than 5 Angstroms thick.
15. The transistor of claim 12 wherein each of the insulator-material regions comprises SiO 2 .
16. The transistor of claim 12 wherein each of the insulator-material regions extends into one of the respective solid source/drain regions.
17. The transistor of claim 16 wherein each of the insulator-material regions extends completely through the respective solid source/drain region orthogonal to the current-flow direction.