Sensing a memory cell
Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
1. A device, comprising:
a memory cell configured to store a logic state;
a sense component configured to determine the logic state stored on the memory cell during a read operation; and
a circuit comprising a first switching component coupled with a first node and a second switching component coupled with the first switching component and the sense component, wherein a gate of the first switching component is coupled with a signal line and a gate of the second switching component is coupled with the first node, the circuit configured to receive a first voltage from the memory cell that is associated with the logic state at the first node and a second voltage at the gate of the first switching component and output a third voltage to the sense component based at least in part on receiving the first voltage at the first node and the second voltage at the gate of the first switching component, wherein the third voltage is less than the first voltage.
2. The device of claim 1 , wherein the first switching component is configured to selectively couple the sense component with the first node during the read operation based at least in part on the logic state stored on the memory cell.
3. The device of claim 2 , wherein the first switching component is configured to selectively couple the sense component with the first node after the memory cell transfers a first charge indicative of a high logic state to the first node.
4. The device of claim 1 , wherein the second switching component is configured to reduce the first voltage associated with the logic state for the sense component during the read operation.
5. The device of claim 1 , wherein:
the first switching component comprises a p-type metal oxide semiconductor (PMOS) field effect transistor (FET) and the second switching component comprises an n-type metal oxide semiconductor (NMOS) field effect transistor (FET); and
the PMOS FET and the NMOS FET are arranged in a serial configuration.
6. The device of claim 5 , wherein the PMOS FET is configured to selectively transfer, based at least in part on the logic state stored on the memory cell and a threshold voltage of the PMOS FET, a charge of the memory cell to the sense component in response to the second voltage being applied to a gate of the PMOS FET.
7. The device of claim 5 , wherein:
the PMOS FET, based at least in part on the second voltage applied to a gate of the PMOS FET, is configured to be activated when a fourth voltage is present at the first node and not to be activated when a fifth voltage is present at the first node; and
the fourth voltage at the first node corresponds to a high logic state of the memory cell and the fifth voltage at the first node corresponds to a low logic state of the memory cell.
8. The device of claim 5 , wherein:
the NMOS FET is configured as a source-follower to down convert the first voltage associated with the logic state to the third voltage that is within an operation voltage of the sense component; and
the third voltage is lower than the first voltage associated with the logic state by an amount corresponding to a threshold voltage of the NMOS FET.
9. The device of claim 1 , wherein the circuit further comprises a third switching component coupled with the sense component and the second switching component, wherein the third switching component is configured to dampen a coupling noise between the sense component and the second switching component.
10. The device of claim 1 , wherein the sense component is configured to operate at a fourth voltage that is lower than a fifth voltage at which the memory cell is configured to operate.
11. The device of claim 1 , wherein:
the circuit is configured to couple the sense component with the memory cell when the memory cell transfers a first charge indicative of a high logic state to the first node during the read operation; and
the circuit is configured to isolate the sense component from the memory cell when the memory cell transfers a second charge indicative of a low logic state to the first node during the read operation.