Word line cache mode
View Patent ↗Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.
1. A semiconductor device comprising:
a plurality of memory cells;
a plurality of word lines that controls operations of the plurality of memory cells;
a plurality of word line drivers that each controls a respective word line of the plurality of word lines, wherein each word line driver of the plurality of word line drivers comprises:
a pull-up transistor to transition a corresponding word line to a logic high voltage; and
a pull-down transistor to transition the corresponding word line to a logic low voltage, wherein the pull-down transistor comprises an n-channel transistor that is activated during an inactive period for the corresponding word line; and
local controls that each controls a respective word line driver of the plurality of word line drivers, wherein the local controls are configured to:
assert a voltage on the corresponding word line of the plurality of word lines;
start an internal timer responsive, at least in part, to assertion of the voltage, wherein the internal timer is configured to provide additional settling of the corresponding word line before activation to reduce channel hot carrier issues for the n-channel transistor;
determine whether the internal timer has elapsed; and
after the internal timer has elapsed, de-assert the voltage from the corresponding word line as a row address strobe timer (tRAS) lockout.
2. The semiconductor device of claim 1 , wherein the internal timer is greater than or equal to a worst case scenario time for a non-write operation via the corresponding word line.
3. The semiconductor device of claim 2 , wherein the internal timer is less than an external timer asserted according to a specification for the semiconductor device.
4. The semiconductor device of claim 1 , wherein the local controls are configured to:
receive a write event during the timer lockout; and
assert a write voltage on the corresponding word line via the respective word line driver.
5. The semiconductor device of claim 4 , wherein the write voltage and the voltage have the same magnitude.
6. The semiconductor device of claim 4 , wherein the write voltage has a greater magnitude than the voltage has.
7. The semiconductor device of claim 4 , wherein the local controls are configured to:
start an internal write timer responsive, at least in part, to assertion of the write voltage;
determine whether the internal write timer has elapsed; and
upon a lapse of the internal write timer, de-assert the write voltage from the corresponding word line.
8. The semiconductor device of claim 7 , wherein a duration of the internal write timer is greater than or equal to a worst case scenario for timing for the write event.
9. A memory device comprising:
a memory cell;
a word line that controls memory operations on the memory cell;
a word line driver that controls the word line; and
a local control that controls the word line via the word line driver, wherein the local controls are configured to:
determine whether an indication of a non-write event is received;
upon receipt of the indication of the non-write event, cause the word line driver to assert a non-write voltage on the word line;
determine whether an indication of a write event is received; and
upon receipt of the indication of the write event, cause the word line driver to assert a write voltage on the word line, wherein the write voltage is greater than the non-write voltage; and
a dynamic voltage supply configured to:
provide the write voltage after a gapped write until a write timer has elapsed, where the gapped write is a first non-pulse location in a write burst where a pulse does not occur after a chain of write pulses; and
otherwise, provide the non-write voltage.
10. The memory device of claim 9 , wherein the indication of the non-write event comprises:
a toggle of an arm signal in the word line driver; and
a lack of write pulses on a write signal.
11. The memory device of claim 9 , wherein the indication of the write event comprises:
a toggle of an arm signal in the word line driver; and
a cessation of write pulses following one or more write pulses on a write signal.
12. The memory device of claim 9 , wherein the local control comprises a voltage driver that selects a selected voltage from a low voltage, the non-write voltage, or the write voltage and causes the word line driver to drive the word line to the selected voltage.
13. The memory device of claim 12 , wherein the local control comprises the dynamic voltage supply that alternates between providing the non-write voltage and providing the write voltage.
14. A memory device comprising:
at least one memory cell;
at least one word line coupled to the at least one memory cell; and
at least one local control that controls the word line and comprises a dynamic voltage supply, wherein the at least one local control is configured to:
receive an indication of a gapped write, wherein the gapped write is a first non-pulse location in a write burst where a pulse does not occur after a chain of write pulses;
in response to the indication, cause the dynamic voltage supply to output an elevated drive voltage;
in response to the indication, start an internal write timer;
determine whether the internal write timer has elapsed; and
in response to the internal write timer elapsing, cause the dynamic voltage supply to output a reduced drive voltage.
15. The memory device of claim 14 , wherein the at least one local control comprises a voltage driver configured to select between the elevated drive voltage, the reduced drive voltage, and a low voltage.
16. The memory device of claim 15 , wherein the at least one local control is configured to:
cause the voltage driver to output the reduced drive voltage during a non-write event;
start an internal non-write timer for the non-write event; and
after the internal non-write timer elapses, cause the voltage driver to output the low voltage.
17. The memory device of claim 15 , wherein the at least one local control is configured to cause the voltage driver to:
cause the voltage driver to output the elevated drive voltage during a write event;
start an internal write timer for the write event; and
after the internal write timer elapses, cause the voltage driver to output the low voltage.