Cross-point memory array and related fabrication techniques
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
1. A method, comprising:
forming a via through a top layer of a stack that comprises a placeholder layer;
forming, using the via, a via hole that extends through the stack in a first direction;
forming, using the via and the via hole, a cavity within the placeholder layer;
filling the cavity with a memory material to form a disc of memory material at the placeholder layer;
removing, after filling the cavity with the memory material to form the disc of memory material, a first portion of the disc of memory material through the via to form a ring of memory material at the placeholder layer, the ring of memory material surrounding a vertical axis of the via that extends in the first direction; and
forming a first channel in the disc of memory material at the placeholder layer by removing a second portion of the memory material, the first channel extending in a second direction different from the first direction and separating the disc of memory material into two discrete elements.
2. The method of claim 1 , wherein forming the first channel comprises:
removing, through a plurality of vias that includes the via, the second portion of the memory material from the placeholder layer.
3. The method of claim 1 , further comprising:
forming a second channel in the memory material, the second channel extending in a third direction and separating each of the two discrete elements to form four discrete elements.
4. The method of claim 3 , wherein each of the four discrete elements has a curved surface.
5. The method of claim 1 , wherein the memory material comprises a chalcogenide material.
6. A method, comprising:
forming a row of vias in a top layer of a stack that comprises a placeholder material at a placeholder layer;
forming, using the row of vias, a plurality of first via holes that each extend through the stack in a vertical direction;
removing, using the row of vias and the first via holes, a portion of the placeholder material to form a first channel in the placeholder material, the first channel extending in a horizontal direction and connecting at least three of the first via holes;
filling the first channel with a memory material;
forming, using the row of vias, a plurality of second via holes that each extend through the stack in the vertical direction;
removing, using the row of vias and the second via holes, a portion of the memory material to form a second channel in the memory material within the first channel, the second channel extending in the horizontal direction and narrower than the first channel; and
filling the second channel with a dielectric material.
7. The method of claim 6 , wherein forming the first channel comprises:
forming a plurality of first cavities in the placeholder material, wherein contiguous first cavities merge to form the first channel.
8. The method of claim 7 , wherein forming the plurality of first cavities comprises:
removing, through the row of vias, a portion of the placeholder material from the placeholder layer.
9. The method of claim 6 , wherein forming the second channel comprises:
removing, through the row of vias, a portion of the memory material from the first channel.
10. The method of claim 6 , wherein filling the second channel with the dielectric material creates a band of memory material that surrounds the dielectric material.
11. The method of claim 6 , further comprising:
forming a third channel at the placeholder layer, wherein the third channel extends in a second horizontal direction and separates the memory material within the first channel into a plurality of memory material elements.
12. The method of claim 11 , wherein forming the third channel comprises:
forming a row of second vias through the top layer of the stack, wherein the row of second vias intersects the row of vias.
13. The method of claim 11 , wherein each memory material element of the plurality of memory material elements is coupled with at least three electrodes.
14. The method of claim 6 , wherein the memory material comprises a chalcogenide material.