Apparatuses and methods for fixing a logic level of an internal signal line
View Patent ↗An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
1. A method comprising:
enabling a register of a semiconductor device, wherein the enabled register is configured to provide data bus inversion information or data mask information to a data terminal of the semiconductor device;
providing, from the register of the semiconductor device, a first control signal to a control circuit of the semiconductor device, the first control signal including information indicative of an operation mode of an error check operation being enabled and an operation mode of a data bus inversion operation being disabled; and
responsive to the first control signal, providing a voltage level of a signal line coupled to an external terminal of the semiconductor device at a constant level, the external terminal configured to receive the data bus inversion information or the data mask information.
2. The method of claim 1 , further comprising:
rendering the signal line into high-impedance at least while the data bus inversion operation is disabled.
3. The method of claim 2 , further comprising:
activating a second enable signal responsive to a read enable signal.
4. The method of claim 3 , further comprising:
issuing a read command, from a controller, to activate the read enable signal.
5. The method of claim 1 , further comprising:
providing, from the register, a second control signal to a control circuit, the second control signal including information indicative of the operation mode of the error check operation being enabled and the operation mode of the data bus inversion operation being disabled.
6. The method of claim 5 , further comprising:
providing a plurality of enable signals responsive to the first and second control signals.
7. The method of claim 6 , further comprising:
activating a first buffer circuit responsive to a first enable signal of the plurality of enable signals; and
providing an output signal of the first buffer circuit to a data line.
8. The method of claim 7 ,
activating second and third enable signals of the plurality of enable signals; and
rendering the signal line to a high voltage level, wherein the first control signal is high and second control signal is high.
9. The method of claim 8 , wherein the operation mode of the error check operation corresponds to an enabled mode and the operation mode of the data bus inversion operation corresponds to an enabled mode.
10. The method of claim 7 , further comprising:
performing the error check operation based, at least in part, on a logic level associated with a provided voltage on the signal line.
11. The method of claim 10 , further comprising:
performing the error check operation further based, at least in part, on data that is provided to a data input/output terminal.
12. The method of claim 11 , wherein the error check operation includes a CRC operation.
13. The method of claim 10 , wherein the error check operation includes an ECC operation.
14. A method comprising:
activating; at a semiconductor device, a read enable signal based on an read command;
responsive to receiving a read enable signal based on the read command, providing first and second mode signals indicative of an operation mode of an error check operation being enabled and an operation mode of a data bus inversion operation being disabled; and
responsive to the first and second mode signals, providing a voltage level of a signal line coupled to an external terminal of the semiconductor device.
15. The method of claim 14 , further comprising:
responsive to the first mode signal indicative of the error check operation being disabled, performing read and write operations on a memory cell array of the semiconductor device.
16. The method of claim 14 , further comprising:
responsive to the first mode signal indicative of the error check operation being enabled, performing read and write operations on a multi-purpose register of the semiconductor device.
17. The method of claim 14 , further comprising:
responsive to the second mode signal indicative of the data bus inversion operation being enabled, providing read to data lines of the semiconductor device; and
providing data bus inversion signals to a parallel/serial conversion circuit coupled to the signal line, wherein the parallel/serial conversion circuit is configured to provide the voltage level to the signal line.
18. The method of claim 14 , wherein responsive to the first mode signal indicative of the error check operation being enabled:
activating a multi-purpose register of the semiconductor device, the multi-purpose register configured to output test data to a buffer circuit of the semiconductor device; and
providing a first enable signal to the buffer circuit; and wherein
responsive to the second mode signal indicative of the data bus inversion operation being disabled, rendering the signal line into high-impedance.
19. The method of claim 14 , further comprising:
enabling a register of the semiconductor device to provide the first and second mode signals.