IP Library Granted Patent US 11,966,329
Granted Patent B2
US 11,966,329 · App. 15/952,087 · Granted Apr 23, 2024

Address map caching for a memory system

Inventor: Alex Frolikov (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F12/0802G06F2212/2022G06F2212/656
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Quick Facts
Patent No.
US 11,966,329
App. No.
15/952,087
Filed
Apr 12, 2018
Granted
Apr 23, 2024
Kind
B2
Art Unit
2139
USPC
711/118
Abstract

A memory system having non-volatile media, a volatile memory, and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The non-volatile media has a quantity of memory units and stores an address map that defines logical addresses used in the requests in terms of physical addresses of the memory units in the non-volatile media. The host system has a memory connected to the memory system via a communication channel. The memory system has a cache manager that stores a first portion of the address map in the volatile memory of the memory system and a second portion of the address map in the memory of the host system. In response to an operation that uses a logical address defined in the second portion, the cache manager retrieves the second portion of the address map from the memory of the host system through the communication channel to the volatile memory of the memory system.

Claims (75)

1. A solid-state drive memory system, comprising:

non-volatile media having a quantity of memory units, wherein the non-volatile media includes a flash memory, and wherein an address map is stored in the non-volatile media;

a volatile memory that stores a first portion of the address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media; and

a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;

wherein a cache manager stores a second portion of the address map in the memory of the host system;

wherein in response to an operation that uses a logical address defined in the second portion, the cache manager is configured to swap the first portion of the address map and the second portion of the address between the volatile memory of the solid-state drive memory system and the memory of the host system by:

retrieving the second portion of the address map from the memory of the host system through the communication channel and storing the second portion of the address map in the volatile memory of the memory system;

transmitting the first portion of the address map from the volatile memory of the memory system through the communication channel to the memory of the host system;

wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media; and

wherein the memory of the host system is identified to the memory system during the powering up via a base address register;

wherein, before the first portion of the address map has been swapped into the memory of the host system, the first portion of the address map is changed or updated:

while the first portion of the address map is stored in the volatile memory of the memory system, and

during first operations involving logical addresses defined in the first portion of the address map, wherein the first operations are performed by the controller responsive to a first request from the host system;

wherein, after the second portion of the address map has been swapped into the volatile memory of the memory system, the second portion of the address map is changed or updated:

while the second portion of the address map is stored in the volatile memory of the memory system, and

during second operations involving logical addresses defined in the second portion of the address map, wherein the second operations are performed by the controller responsive to a second request from the host system;

wherein, after the second portion of the address map has been swapped into the volatile memory of the memory system and the first portion of the address map has been swapped into the memory of the host system, in response to a request to shut down the memory system, the cache manager stores, in the non-volatile media of the memory system, the second portion of the address map from the volatile memory of the memory system that has been changed or updated during the second operations; and

wherein further in response to the request to shut down the memory system, the cache manager stores, in the non-volatile media of the memory system, the first portion of the address map from the memory of the host system that has been changed or updated during the first operations, such that changes to both of the first portion and the second portion of the address map resulting from the first operations and the second operations, respectively, are saved in the address map stored in the non-volatile memory upon shutdown of the memory system;

wherein the controller is configured to perform, in response to a first request associated with the first operations, a real time analysis of data stored in the memory of the memory system, wherein the data stored in the memory of the memory system comprises sensor data collected from a plurality of sensors, and wherein the plurality of sensors are real time sensors connected to the memory system;

wherein the controller is configured to determine, based on the real time analysis, a reduced data set responsive to the first request; and

wherein the controller is configured to communicate the reduced data set to the host system.

2. The memory system of claim 1 , wherein the first portion of the address map is updated during at least write operations made using logical addresses defined in the first portion of the address map.

3. The memory system of claim 2 , wherein the host system and the memory system communicate over the communication channel in accordance with a communication protocol for peripheral component interconnect express bus.

4. The memory system of claim 2 , wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media.

5. The memory system of claim 1 , wherein during powering up the memory system, the cache manager copies the first portion of the address map from the non-volatile media to the volatile memory and the second portion of the address map from the non-volatile media to the memory of the host system.

6. The memory system of claim 1 , wherein the memory of the host system includes message queues for communications between the host system and the memory system.

7. The memory system of claim 1 , wherein the controller only processes the requests from the host system using address map portions that are stored on the volatile memory.

8. The memory system of claim 1 , wherein the controller does not process the requests from the host system using address map portions that are stored in the memory of the host system.

9. A method, comprising:

storing, in non-volatile media of a memory system having a quantity of memory units, an address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media;

loading, by a cache manager of the memory system, a first portion of the address map in a volatile memory of the memory system;

processing, by a controller of the memory system, requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;

loading, by the cache manager, a second portion of the address map in the memory of the host system;

changing or updating, during first operations involving logical addresses defined in the first portion of the address map stored in the volatile memory of the memory system, the first portion of the address map stored in the volatile memory of the memory system;

after the changing or updating of the first portion of the address map stored in the volatile memory of the memory system, and in response to an operation that uses a logical address defined in the second portion, the cache manager is configured to swap the first portion of the address map and the second portion of the address between the volatile memory of the solid-state drive memory system and the memory of the host system by:

retrieving the second portion of the address map from the memory of the host system through the communication channel and storing the second portion of the address map in the volatile memory of the memory system;

transmitting, by the cache manager, the first portion of the address map from the volatile memory of the memory system through the communication channel to the memory of the host system; and

identifying, during the powering up, the memory of the host system via a base address register;

after the second portion of the address map is swapped into the volatile memory of the memory system, changing or updating, during second operations involving logical addresses defined in the second portion of the address map, the second portion of the address map;

receiving, at the cache manager a request to shut down the memory system; and

after the second portion of the address map is swapped into the volatile memory of the memory system, storing, in the non-volatile media of the memory system by the cache manager in response to the request, the second portion of the address map from the volatile memory of the memory system that has been changed or updated during the second operations; and

after the first portion of the address map is swapped into the memory of the host system, storing, in the non-volatile media of the memory system by the cache manager in response to the request, the first portion of the address map from the memory of the host system that has been changed or updated during the first operations;

wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media;

wherein the non-volatile media includes a flash memory and the memory system is a solid-state drive;

performing, by the controller in response to a first request associated with the first operations, a real time analysis of data stored in the memory of the memory system, wherein the data stored in the memory of the memory system comprises sensor data collected from a plurality of sensors, and wherein the plurality of sensors are real time sensors connected to the memory system;

determining, by the controller based on the real time analysis, a reduced data set responsive to the first request; and

communicating, by the controller, the reduced data set to the host system.

10. The method of claim 9 , wherein the host system and the memory system communicate over the communication channel in accordance with a communication protocol for peripheral component interconnect express bus; and the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media.

11. The method of claim 10 , further comprising:

during powering up the memory system, copying by the cache manager the first portion of the address map from the non-volatile media to the volatile memory and the second portion of the address map from the non-volatile media to the memory of the host system.

12. The method of claim 9 , further comprising:

receiving, from message queues formed on the memory of the host system, the requests from the host system to store data in the non-volatile media or retrieve data from the non-volatile media, wherein the requests identify memory locations using the logical addresses defined using the address map in terms of the physical addresses of the memory units in the non-volatile media.

13. The method of claim 9 , wherein the loading, by the cache manager of the memory system, of the first portion of the address map in the volatile memory of the memory system comprises caching a most frequently used portion of the address map as the first portion of the address map in the volatile memory of the memory system.

14. A non-transitory computer storage medium storing instructions which, when executed by a memory system having non-volatile media, a volatile memory, and a controller, cause the memory system to perform a method, the method comprising:

storing, in the non-volatile media having a quantity of memory units, an address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media;

loading a first portion of the address map in a volatile memory of the memory system;

loading a second portion of the address map in the memory of the host system;

processing requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;

in response to a first operation that uses a first logical address defined in the first portion of the address map in the volatile memory of the memory system, obtaining a first relevant address definition from the first portion of the address map stored in the volatile memory of the memory system;

completing the first operation using the first relevant address definition from the first portion;

in response to a second operation that uses a second logical address defined in the second portion of the memory of the host system, obtaining via the communication channel a second relevant address definition from the second portion of the address map stored in the memory of the host system;

completing the second operation using the second relevant address definition from the second portion;

changing or updating, during first operations involving logical addresses defined in the first portion of the address map stored in the volatile memory of the memory system, the second portion of the address map stored in the volatile memory of the memory system;

changing or updating, during second operations involving logical addresses defined in the second portion of the address map cached in the memory of the host system, the second portion of the address map cached in the memory of the host system;

receiving, at the cache manager a request to shut down the memory system;

in the non-volatile media of the memory system by the cache manager in response to the request, storing:

the first portion of the address map from the volatile memory of the memory system that has been changed or updated during the first operations, and

the second portion of the address map from the host system that has been changed or updated during the second operations;

wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media;

performing, in response to a first request associated with the first operations, a real time analysis of data stored in the memory of the memory system, wherein the data stored in the memory of the memory system comprises sensor data collected from a plurality of sensors, and wherein the plurality of sensors are real time sensors connected to the memory system;

determining, based on the real time analysis, a reduced data set responsive to the first request; and

communicating the reduced data set to the host system.

15. The non-transitory computer storage medium of claim 14 , wherein the method further comprises:

identifying, during powering up of the memory system, the memory of the host system via a base address register; and

receiving, from message queues formed on the memory of the host system, the requests from the host system to store data in the non-volatile media or retrieve data from the non-volatile media, wherein the requests identify memory locations using the logical addresses defined using the address map in terms of the physical addresses of the memory units in the non-volatile media.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2018
From: FROLIKOV, ALEX
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046978/0190 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Continuity (1)
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