IP Library Granted Patent US 9,997,398
Granted Patent B2
US 9,997,398 · App. 15/684,741 · Granted Jun 12, 2018

Methods of forming one or more covered voids in a semiconductor substrate

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Quick Facts
Patent No.
US 9,997,398
App. No.
15/684,741
Granted
Jun 12, 2018
Kind
B2
Abstract

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Claims (26)

1. A method of forming a semiconductor-on-insulator substrate, comprising:

providing a base region of a base substrate, a silicon-containing semiconductor region over the base region, and an insulative layer over the silicon-containing semiconductor region;

etching trenches into the insulative layer to the silicon-containing semiconductor region;

selectively growing relative to the insulative layer a bridging material over the insulative layer effective to bridge across the trenches with bridging material and form covered elongated trenches;

providing a release region intermediate the silicon-containing semiconductor region and the base region of the base substrate;

at an interface of the release region and the silicon-containing semiconductor region, separating a) the base region and release region from b) the silicon-containing semiconductor region, the insulative layer with the covered elongated trenches, and the bridging material;

forming first field effect transistor gates within the covered elongated trenches; and

forming second field effect transistor gates opposite the first field effect transistor gates over the silicon-containing semiconductor region, and forming field effect transistor channel regions within material of the silicon-containing semiconductor region received between the first and second field effect transistor gates.

2. The method of claim 1 comprising forming field effect transistor source/drain regions within the silicon-containing semiconductor region.

3. The method of claim 1 forming an insulator layer on an outer surface of the bridging material bridging across the trenches.

4. The method of claim 3 comprising bonding the insulator layer to a carrier substrate after said separating.

5. The method of claim 1 comprising epitaxially growing an elemental-form silicon-comprising material from bases of the trenches while selectively growing the bridging material over the insulator layer effective to bridge across the trenches.

6. The method of claim 1 wherein the selectively growing comprises growing elemental-form silicon-comprising material.

7. The method of claim 6 wherein the selectively growing forms the bridging material to comprise polysilicon.

8. The method of claim 7 further comprising oxidizing the silicon-comprising material to form the bridging material to comprise silicon dioxide.

9. The method of claim 1 comprising providing an exposed epitaxial seed material proximate tops of the trenches over the insulative material prior to the selectively growing, the selectively growing comprising epitaxial growing an elemental-form silicon-comprising material to bridge across the trenches.

10. The method of claim 9 comprising providing the exposed epitaxial seed material to comprise elemental-form silicon.

11. The method of claim 10 comprising providing the exposed epitaxial seed material to comprise elemental-form monocrystalline silicon.

12. The method of claim 9 comprising providing the exposed epitaxial seed material to comprise any one or more of elemental-form W or a silicide.

13. The method of claim 1 comprising forming the release region before the etching.

14. The method of claim 13 wherein the forming the release region comprises implanting hydrogen into the base substrate.

15. The method of claim 13 wherein the forming the release region comprises implanting oxygen into the base substrate.

16. The method of claim 13 wherein the forming the release region comprises depositing an insulator layer over the base region, and prior to providing the silicon-containing semiconductor region.

17. The method of claim 1 comprising forming the release region after the etching.

18. The method of claim 17 wherein the forming the release region comprises implanting hydrogen into the base substrate.

19. The method of claim 17 wherein the forming the release region comprises implanting oxygen into the base substrate.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →