Methods for on-die memory termination and memory devices and systems employing the same
Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.
1. A method of operating a memory system, comprising:
receiving a first command instructing a first portion of the memory system to perform a first communication with a memory host;
transmitting, from the first portion of the memory system to a second portion of the memory system, a signal instructing the second portion to enter an on-die termination mode; and
performing, with the first portion, the first communication while the second portion is in the on-die termination mode,
wherein an impedance level of the on-die termination mode is indicated by either a voltage or a duration of the signal, and
wherein the first command does not include a second indication on a second chip select terminal of the second memory device that the second portion is not targeted by the first command.
2. The method of claim 1 , wherein the second portion exits the on-die termination mode after the first communication is completed.
3. The method of claim 1 , wherein the transmitting of the signal occurs on a first on-die termination terminal of the first portion electrically connected to a second on-die termination terminal of the second portion.
4. The method of claim 3 , wherein the first and second on-die termination terminal are input/output terminals.
5. The method of claim 1 , wherein the first command includes a first indication on a first chip select terminal of the first memory device that the first portion is targeted by the first command.
6. The method of claim 1 , wherein the first communication is one of a read or a write operation.
7. The method of claim 1 , wherein a single semiconductor die comprises the first portion of the memory system and the second portion of the memory system.
8. A memory system, comprising:
a first memory device including a first on-die termination terminal; and
a second memory device including a second on-die termination terminal electrically coupled to the first on-die termination terminal;
wherein the first memory device includes first circuitry configured to:
receive a first command instructing the first memory device to perform a first communication with a memory host;
transmit, based at least in part on the first command, a signal at the first on-die termination terminal instructing the second memory device to enter an on-die termination mode, and
wherein an impedance level of the on-die termination mode is indicated by either a voltage or a duration of the signal, and
wherein the first command does not include a second indication on a second chip select terminal of the second memory device that the second portion is not targeted by the first command.
9. The memory system of claim 8 , wherein the second memory device includes second circuitry configured to:
enter the on-die termination mode based at least in part on receiving the signal at the second on-die termination terminal.
10. The memory system of claim 9 , wherein the second circuitry is further configured to exit the on-die termination mode after the first communication is completed.
11. The memory system of claim 8 , wherein the first and second on-die termination terminal are input/output terminals.
12. The memory system of claim 8 , wherein a single semiconductor die comprises the first memory device and the second memory device.
13. A method of operating a memory system, comprising:
transmitting a first command instructing a first portion of the memory system to perform a first communication with a memory host; and
performing the first communication with the first portion of the memory system while a second portion of the memory system operates in an on-die termination mode that is based at least in part on a signal transmitted from the first portion of the memory system to the second portion of the memory system,
wherein an impedance level of the on-die termination mode is indicated by either a voltage or a duration of the signal, and
wherein the first command is exclusive of an indication on a second chip select terminal of the second portion.
14. The method of claim 13 , wherein the first command includes a first indication at a first chip select terminal of the first portion that the first portion is targeted by the first command.
15. The method of claim 13 , wherein the first communication comprises at least one of a read operation or a write operation.
16. The method of claim 13 , wherein a single semiconductor die comprises the first portion of the memory system and the second portion of the memory system.