Apparatuses and methods for semiconductor circuit layout

1. An apparatus comprising:

a transistor area comprising at least one n-channel transistor and at least one p-channel transistor, the at least one n-channel transistor and the at least one p-channel transistor being disposed relative to each other in a first direction;

a resistor area comprising at least one resistor, the resistor area being disposed relative to the transistor area in a second direction, the second direction crossing the first direction; and

a delay circuit comprising a logic circuit and the at least one resistor coupled to the logic circuit, wherein the at least one resistor is disposed relative to the logic circuit in the second direction crossing the first direction;

wherein the logic circuit is between the at least one n-channel transistor and the at least one p-channel transistor in the first direction, and wherein the at least one resistor extending in the first direction greater than a size of the logic circuit.

2. The apparatus of claim 1 , wherein the at least one resistor is greater in length than a size of the transistor area in the second direction.

3. The apparatus of claim 1 , further comprising a substrate-contact area and a well-contact area;

wherein the transistor area is disposed between the substrate-contact area and the well-contact area.

4. The apparatus of claim 3 , wherein one of the substrate-contact area and the well-contact area is elongated in the second direction to provide an elongated portion, the elongated portion being disposed relative to the resistor region in the first direction.

5. The apparatus of claim 4 , wherein the third circuit and a fourth circuit are arranged in line in the first direction to form a third arrangement.

6. The apparatus of claim 1 , further comprising an additional transistor area, the additional transistor area being disposed relative to the transistor area in the first direction and comprising at least one additional n-channel transistor and at least one additional p-channel transistor, and the at least one additional n-channel transistor and the at least one additional p-channel transistor being disposed relative to each other in a first direction.

7. The apparatus of claim 6 , wherein the at least one resistor comprises a first portion and a second portion, the first portion being disposed relative to the transistor area in the second direction, and the second portion being disposed relative to the additional transistor area in the second direction.

8. The apparatus of claim 6 , wherein the resistor area further comprises an additional resistor extending the first direction.

9. The apparatus of claim 8 ,

wherein the at least one resistor is greater in length than a size of the transistor area in the second direction; and

wherein the additional resistor is greater in length than a size of the additional transistor area in the second direction.

10. The apparatus of claim 6 , further comprising a first substrate-contact, a well-contact area and a second substrate-contact area, the well-contact area being shared by the transistor area and the additional transistor area;

wherein the transistor area is disposed between the first substrate-contact area and the well-contact area; and

wherein the additional transistor area is disposed between the well-contact area and the second substrate-contact area.

11. The apparatus of claim 6 , further comprising a first well-contact, a substrate-contact area and a second well-contact area, the substrate-contact area being shared by the transistor area and the additional transistor area;

wherein the transistor area is disposed between the first well-contact area and the substrate-contact area; and

wherein the additional transistor area is disposed between the substrate-contact area and the second well-contact area.

12. The apparatus of claim 1 , wherein the first direction and the second direction are substantially perpendicular to each other.

13. An apparatus comprising:

a first substrate-contact area;

a first well-contact area disposed relative to the substrate-contact area in a first direction; and

a first delay circuit comprising a first logic circuit and a first resistor coupled to the first logic circuit;

wherein the first logic circuit is between the first substrate-contact area and the first well-contract area in the first direction;

wherein the first resistor is disposed relative to the first logic circuit in a second direction crossing the first direction; and

wherein the first resistor extending in the first direction greater than a size of the first logic circuit.

14. The apparatus of claim 13 , further comprising:

a second substrate-contact area disposed relative to the first well-contact area in the first direction; and

a second delay circuit comprising a second logic circuit and a second resistor coupled to the second logic circuit;

wherein the second logic circuit is between the first well-contract area and the second substrate-contact area in the first direction;

wherein the second resistor is disposed relative to the first resistor in the second direction; and

wherein the second resistor extending in the first direction greater than a size of the second logic circuit.

15. The apparatus of claim 14 ,

wherein the first resistor extends across the first and second logic circuits; and

wherein the second resistor extends across the first and second logic circuits.

16. The apparatus of claim 14 , further comprising:

a substrate region of a first conductivity type; and

a well region of a second conductivity type selectively formed in the substrate region to define first and second portions in the substrate region;

wherein the first and second substrate-areas are coupled to the first and second portions of the substrate region, respectively;

wherein the first well-contact area is coupled to the well region;

wherein the first logic circuit includes a first transistor formed in the first portion of the substrate region and a second transistor formed in the well region; and

wherein the second logic circuit includes a third transistor formed in the second portion of the substrate region and a fourth transistor formed in the well region.

17. The apparatus of claim 13 , further comprising:

a second well-contact area disposed relative to the first substrate-contact area in the first direction; and

a second delay circuit comprising a second logic circuit and a second resistor coupled to the second logic circuit;

wherein the second logic circuit is between the first substrate-contract area and the second well-contact area in the first direction;

wherein the second resistor is disposed relative to the first resistor in the second direction; and

wherein the second resistor extending in the first direction greater than a size of the second logic circuit.

18. The apparatus of claim 17 ,

wherein the first resistor extends across the first and second logic circuits; and

wherein the second resistor extends across the first and second logic circuits.

19. The apparatus of claim 17 , further comprising:

a substrate region of a first conductivity type; and

first and second well regions selectively formed in the substrate region to define a portion of the substrate region therebetween;

wherein the first substrate-area is coupled to the portion of the substrate region;

wherein the first and second well-contact areas are coupled to the first and second well regions, respectively;

wherein the first logic circuit includes a first transistor formed in the portion of the substrate region and a second transistor formed in the first well region; and

wherein the second logic circuit includes a third transistor formed in the portion of the substrate region and a fourth transistor formed in the second well region.