Simulating access lines

1. A method comprising:

receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to the first access line and a second number of sense lines, wherein each of the memory cells of the first number of sense lines are separated from another memory cell of the first number of sense lines by at least one memory cell of the second number of sense lines;

merging the first bit-vector and the second bit vector into a format associated with storing the first bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines and storing the second bit-vector in a number of memory cells coupled to a second access line and the third number of sense lines; and

performing an operation on the first bit-vector and the second bit-vector.

2. The method of claim 1 , wherein each of the memory cells of the third number of sense lines are adjacent to another of the memory cells of the third number of sense lines.

3. The method of claim 1 , wherein performing the operation comprises performing at least one of a number of AND operations, OR operations, SHIFT operations, INVERT operations, and XOR operations without a sense line address access.

4. The method of claim 3 , wherein performing the at least one of the number of AND, OR, SHIFT, INVERT, XOR operations comprises performing the at least one of the number of AND, OR, SHIFT, INVERT, XOR operations using sensing circuitries coupled to respective columns of complementary sense lines, and wherein each of the sensing circuitries includes a sense amplifier comprising a primary latch and a compute component comprises a secondary latch.

5. The method of claim 1 , wherein the format corresponds to a logical organization of the first access line and the third number of sense lines and the second access line and the third number of sense lines.

6. The method of claim 5 , wherein storing the first bit-vector in a number of physical memory cells coupled to the first access line and the first number of sense lines comprises modifying the format associated with physical storing of the first bit-vector and logically storing the first bit-vector in a number of memory cells coupled to the first access line and the third number of sense lines.

7. The method of claim 1 , wherein performing the operation on the first bit-vector and the second bit-vector comprises performing, in parallel, logical operations between respective bits of the first bit-vector and the second bit-vector.

8. The method of claim 1 , further comprising storing at least a portion of the first bit-vector in the number of physical memory cells that are coupled to the first access line and a first, third, fifth, and seventh ordered sense lines of the number of sense lines.

9. The method of claim 8 , further comprising storing the second bit-vector in the number of memory cells coupled to the first access line and a second, fourth, sixth, and eighth ordered sense lines of the number of sense lines.

10. The method of claim 8 , wherein the method includes storing the first bit-vector in physical memory cells that are each separated from another of the memory cells storing the first bit-vector by each of the memory cells storing the second bit-vector.

11. The method of claim 1 , further comprising storing at least a portion of the first bit-vector in the number of physical memory cells that are coupled to the first access line and a first, second, fifth, and sixth ordered sense lines of the number of sense lines.

12. The method of claim 11 , further comprising storing the second bit-vector in the number of memory cells coupled to the first access line and a third, fourth, seventh, and eighth ordered sense lines of the number of sense lines.

13. The method of claim 1 , further comprising:

receiving a third bit-vector in a format associated with storing the third bit-vector in memory cells coupled to a second access line and the first number of sense lines; and

merging the third bit-vector in memory cells coupled to a third access line and the first number of sense lines.

14. An apparatus comprising:

a first group of memory cells coupled to a first access line and a number of first sense lines in a memory array and configured to store a first bit-vector;

a second group of memory cells coupled to the first access line and a number of second sense lines in the memory array and configured to store a second bit-vector; and

a controller configured to operate sensing circuitry to:

logically merge each respective memory cell of the number of second sense lines to be aligned with sensing circuitry of a respective memory cell of the number of first sense lines; and

perform an operation on the first bit-vector and the second bit-vector.

15. The apparatus of claim 14 , wherein a bit width of the second bit-vector is less than a quantity of memory cells coupled to the first access line.

16. The apparatus of claim 14 , wherein performing the operation comprises performing the operation on a first bit of the first bit-vector stored in a memory cell coupled to the first access line and a first of the number of first sense lines and a first bit of the second bit-vector logically merged to be associated with a corresponding sensing circuitry coupled to the first of the number of first sense lines.

17. A method, comprising:

mapping each respective bit of a first bit-vector to each respective bit of a second bit-vector;

wherein:

the first bit-vector is stored in a first group of memory cells coupled to a number of first sense lines and to an access line of a memory array; and

the second bit-vector is stored in a second group of memory cells coupled to a number of second sense lines and the access line of the memory array;

performing an operation on:

the first bit-vector; and

the second bit-vector;

wherein the operation is performed using sensing circuitry comprising transistors formed on pitch with the memory cells of the memory array.

18. The method of claim 17 , wherein mapping comprises shifting the first bit-vector from sensing circuitry coupled to the number of first sense lines to sensing circuitry coupled to the number of second sense lines.

19. The method of claim 18 , wherein a quantity of the number of first sense lines is a power of two and the quantity of the number of second sense lines is a power of two.

20. The method of claim 18 , wherein the first bit-vector is shifted a quantity of bit positions that is associated with a quantity of the number of first sense lines and a quantity of the number of second sense lines.