Simulating access lines
View Patent ↗Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.
1. An apparatus comprising:
a processor-in-memory (PIM) device, comprising:
a controller;
a first group of memory cells coupled to a first access line and a number of first sense lines in a memory array and configured to store a first bit-vector, wherein the first bit-vector comprises a first group of data values; and
a second group of memory cells coupled to the first access line and a number of second sense lines in the memory array and configured to store a second bit-vector, wherein the second bit-vector comprises a second group of data values;
wherein the controller is configured to operate sensing circuitry to:
shift bits of the first bit-vector to be associated with each corresponding bit of the second bit-vector; and
send the shifted bits of the first bit-vector to a host that is external to the PIM device.
2. The apparatus of claim 1 , wherein the controller configured to shift the bits of the first bit-vector comprises the controller configured to perform at least one of a number of AND operations, OR operations, SHIFT operations, INVERT operations, and XOR operations without a sense line address access.
3. The apparatus of claim 1 , wherein the host comprises a number of external processing resources.
4. The apparatus of claim 3 , wherein the number of processing resources is one processor.
5. The apparatus of claim 1 , wherein the sensing circuitry are coupled to respective columns of complementary sense lines, and wherein each portion of the sensing circuitry corresponding to the columns of complementary sense lines includes a sense amplifier comprising a primary latch and a compute component comprises a secondary latch.
6. The apparatus of claim 1 , wherein the controller is configured to shift a first bit of the first bit-vector stored in a memory cell coupled to the first access line and a first of the number of first sense lines and a first bit of the second bit-vector shifted to be stored in a corresponding sensing circuitry coupled to the first of the number of first sense lines.
7. A method, comprising:
receiving, from a processing resource that is external to a memory device comprising sensing circuitry coupled to a memory array, an instruction to be executed by the memory device;
executing the instruction in a controller of the memory device, wherein executing the instruction includes:
shifting, using the instructions, a first bit-vector stored in a first group of memory cells coupled to a number of first sense lines and to an access line of the memory array, wherein the first bit-vector comprises a first group of data values;
subsequent to shifting the first bit-vector, performing an operation, controlled by the controller using the sensing circuitry coupled to the memory array, on:
the first bit-vector; and
a second bit-vector stored in a second group of memory cells coupled to a number of second sense lines and the access line of the memory array, wherein the second bit-vector comprises a second group of data values.
8. The method of claim 7 , wherein the first bit-vector is shifted from sensing circuitry coupled to the number of first sense lines.
9. The method of claim 8 , wherein the first bit-vector is shifted to sensing circuitry coupled to the number of second sense lines.
10. The method of claim 7 , wherein a quantity of the number of first sense lines is a power of two and the quantity of the number of second sense lines is a power of two.
11. The method of claim 7 , wherein the first bit-vector is shifted a quantity of bit positions that is associated with a quantity of the number of first sense lines and a quantity of the number of second sense lines.
12. The method of claim 11 , wherein the quantity of bit positions associated with each of the first bit-vector and the second bit-vector is equal to half the quantity of the number of first sense lines.
13. An apparatus comprising:
a processor-in-memory (PIM) device comprising:
a controller;
a first number of memory cells coupled to a number of first sense lines and to an access line, wherein the first number of memory cells are configured to store a first bit-vector comprising a first group of data values;
a second number of memory cells coupled to a number of second sense lines and to the access line, wherein the second number of memory cells are configured to store a second bit-vector comprising a second group of data values;
wherein the controller is configured to operate sensing circuitry to:
receive the first bit-vector;
shift the first bit-vector;
perform a number of operations on corresponding bits of the first bit-vector and the second bit-vector in parallel; and
send a result of the number of operations to a host external to the PIM.
14. The apparatus of claim 13 , wherein the controller is further configured to send a resultant first bit-vector and a resultant second bit-vector resulting from performing the number of operations on the first bit-vector and the second bit-vector.
15. The apparatus of claim 13 , wherein the host comprises a number of processing resources.
16. The apparatus of claim 15 , wherein the controller is further configured to receive instructions to store a simulated bit from a simulated access line i in the sensing circuitry from the host.
17. The apparatus of claim 16 , wherein the controller is further configured to store a bit from the first bit-vector in the sensing circuitry coupled to access line └i/2┘ to store the simulated bit from the simulated access line i.
18. The apparatus of claim 13 , wherein the controller is configured to operate sensing circuitry to shift the first bit-vector by shifting portions of the first bit-vector in parallel.
19. The apparatus of claim 13 , wherein the controller is further configured to shift each of the bits from the first bit-vector to sensing circuitry coupled to access line i mod 2 to shift the first bit-vector.
20. The apparatus of claim 13 , wherein:
the first number of memory cells and the second number of memory cells are part of an array having c sense lines and r access lines and that simulates an array having c/2 sense lines and 2r access lines;
the c sense lines include the number of first sense lines and the number of second sense lines and wherein the r access lines include the number of access lines.