Patent Assignment
Reel/Frame 043483/0686
Supplement No. 5 to Patent Security Agreement
Recorded: 2017-08-08
Pages: 22
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2017-07-21
Assignee
U.S. BANK NATIONAL ASSOCIATION
800 NICOLLET MALL, MINNEAPOLIS, MINNESOTA, 55402
Covered Properties
(226)
Semiconductor Devices Comprising Nickel- and Copper-Containing Interconnects
Buried Low-Resistance Metal Word Lines for Cross-Point Variable-Resistance Material Memories
Methods of Forming Through Substrate Interconnects
Methods for Isolating Portions of a Loop of Pitch-Multiplied Material and Related Structures
Systems and Methods to Determine Kinematical Parameters using RFID Tags
Memory Devices Including Capacitor Structures Having Improved Area Efficiency
Multi-Mode Memory Device and Method Having Stacked Memory Dice, a Logic Die and a Command Processing Circuit and Operating in Direct and Indirect Modes
Adaptive Content Inspection
Methods of Forming Vertical Field-Effect Transistor with Selfaligned Contacts for Memory Devices with Planar Periphery/Array and Intermediate Structures Formed Thereby
Current Sense Amplifiers, Memory Devices and Methods
Solid State Lighting Devices with Improved Contacts and Associated Methods of Manufacturing
Memory Devices with a Connecting Region Having a Band Gap Lower Than a Band Gap of a Body Region
Semiconductor Apparatus with Multiple Tiers, and Methods
Methods, Apparatuses, and Circuits for Programming a Memory Device
Solid-State Radiation Transducer Devices Having at Least Partially Transparent Buried-Contact Elements, and Associated Systems and Methods
Method, System, and Device for L-Shaped Memory Component
Application:
15/598,051 →
Publication:
US US20170324032A1
Methods, Articles, and Devices for Pulse Adjustment to Program a Memory Cell
Circuits, Apparatuses, and Methods for Frequency Division
Methods of Operating a Memory Device Comparing Input Data to Data Stored in Memory Cells Coupled to a Data Line
Methods of Manufacturing Stacked Semiconductor Die Assemblies with High Efficiency Thermal Paths
Apparatuses and Methods for Memory Operations Having Variable Latencies
Counter Operation in a State Machine Lattice
Methods of Operating Memory Including Receipt of Ecc Data
Removing Polysilicon
Semiconductor Device Structures
Magnetic Structures, Semiconductor Structures, and Semiconductor Devices
Apparatuses and Methods for Memory Operations Having Variable Latencies
Apparatuses and Methods for Providing Data to a Configurable Storage Area
Apparatuses and Methods for Controlling Data Timing in a Multi-Memory System
Overflow Detection and Correction in State Machine Engines
Flexible Memory System with a Controller and a Stack of Memory
Resistance Variable Memory Sensing Using Programming Signals
Thermally Optimized Phase Change Memory Cells and Methods of Fabricating the Same
Three Dimensional Memory Array with Select Device
Methods and Apparatuses for Providing a Program Voltage Responsive to a Voltage Determination
Apparatuses and Methods for Performing Multiple Memory Operations
Memory Cells Having a Number of Conductive Diffusion Barrier Materials and Manufacturing Methods
Semiconductor Constructions
Apparatus and Methods for Leakage Current Reduction in Integrated Circuits
Memory System Data Management
Methods of Forming Nanostructures Having Low Defect Density
Apparatuses and Methods for Parity Determination Using Sensing Circuitry
Read Threshold Calibration for Ldpc
Apparatus for Power Management
Memory Cell Materials and Semiconductor Device Structures
Apparatuses and Methods of Reading Memory Cells Based on Response to a Test Pulse
Operational Signals Generated from Stored Charge
Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices
Method and Apparatus for Controlling Access to a Common Bus by Multiple Components
Apparatuses and Methods of Entering Unselected Memories into a Different Power Mode During Multi-Memory Operation
Data Movement Between Volatile and Non-Volatile Memory in a Read Cache Memory
Methods of Forming Memory Arrays
Apparatuses and Methods for Concurrently Accessing Different Memory Planes of a Memory
Memory Cells Including Dielectric Materials, Memory Devices Including the Memory Cells, and Methods of Forming Same
Apparatuses and Methods Using Dummy Cells Programmed to Different States
Apparatuses and Methods for Compensating for Process, Voltage, and Temperature Variation in a Memory
Performing Logical Operations Using Sensing Circuitry
Performing Logical Operations Using Sensing Circuitry
Apparatuses and Methods for Voltage Buffering
Device Having Internal Voltage Generating Circuit
System and Method for Duty Cycle Correction
Clock Signal and Supply Voltage Variation Tracking
Bond Pad with Micro-Protrusions for Direct Metallic Bonding
Apparatuses and Methods for Adjusting Timing of Signals
Devices for Time Division Multiplexing of State Machine Engine Signals
Threshold Voltage Margin Analysis
High Performance Memory Controller
Semiconductor Device Including Amplifier
Systems and Devices for Accessing a State Machine
Apparatuses and Methods for Performing Corner Turn Operations Using Sensing Circuitry
Face Down Dual Sided Chip Scale Memory Package
Vertical Bit Vector Shift in Memory
Simulating Access Lines
Methods of Operating Ferroelectric Memory Cells, and Related Ferroelectric Memory Cells and Capacitors
Semiconductor Memory Device Including Output Buffer
Memory Cells
Multi Channel Memory with Flexible Code-Length Ecc
Refresh Circuitry
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Devices Including Memory Arrays, Row Decoder Circuitries and Column Decoder Circuitries
Apparatuses and Methods for Arbitrating a Shared Terminal for Calibration of an Impedance Termination
Constructions Comprising Stacked Memory Arrays
Memory Cells Having a Controlled-Conductivity Region
Methods of Making Semiconductor Device Packages and Related Semiconductor Device Packages
Memory Having a Static Cache and a Dynamic Cache
Integrated Circuit Structures Comprising Conductive Vias And Methods Of Forming Conductive Vias
Apparatuses and Methods for Power Regulation Based on Input Power
Method of Forming Conductive Material of a Buried Transistor Gate Line and Method of Forming a Buried Transistor Gate Line
Integrated Structures
Apparatuses and Methods for Detecting Frequency Ranges Corresponding to Signal Delays of Conductive Vias
Power Reduction for a Sensing Operation of a Memory Cell
Stack Access Control for Memory Device
Apparatuses and Methods for Shifting Data
Apparatuses and Methods for Photonic Communication and Photonic Addressing
Methods of Forming Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material
Ferroelectric Memory Cell Recovery
Accessing Data in Memory
Patent:
9,997,212 →
Application:
15/494,879 →
Memory Apparatus with Redundancy Array
Apparatuses and Methods for Mixed Charge Pumps with Voltage Regulator Circuits
Methods Of Forming An Elevationally Extending Conductor Laterally Between A Pair Of Conductive Lines
Array Data Bit Inversion
Memory Devices and Methods of Their Operation During a Programming Operation
Patent:
9,805,801 →
Application:
15/499,119 →
Methods and Apparatuses Including Command Delay Adjustment Circuit
Methods of Operating Memory Under Erase Conditions
Magnetic Tunnel Junctions
Apparatuses Having Body Connection Lines Coupled with Access Devices
Application:
62/525,106 →
Memory Cell Imprint Avoidance
Column Repair in Memory
Patent:
10,068,664 →
Application:
15/600,409 →
Shift Skip
Patent:
10,013,197 →
Application:
15/611,369 →
Semiconductor Device Assembly with Die Support Structures
Array Of Elevationally-Extending Transistors And A Method Used In Forming An Array Of Elevationally-Extending Transistors
Application:
62/508,935 →
Apparatuses and Methods for Simultaneous in Data Path Compute Operations
Error Detection Code Hold Pattern Synchronization
Storing Data Elements of Different Lengths in Respective Adjacent Rows or Columns According to Memory Shapes
Apparatuses Comprising Semiconductor Dies in Face-to-Face Arrangements
Patent:
10,115,709 →
Application:
15/644,383 →
Structure Of Integrated Circuitry And A Method Of Forming A Conductive Via
Patent:
9,960,114 →
Application:
15/585,396 →
Semiconductor Devices with Back-Side Coils for Wireless Signal and Power Coupling
Semiconductor Devices with Through-Substrate Coils for Wireless Signal and Power Coupling
Application:
15/584,310 →
Publication:
US US20180323253A1
Bank to Bank Data Transfer
Data Transfer Between Subarrays in Memory
Apparatuses Including Test Segment Circuits Having Latch Circuits for Testing a Semiconductor Die
Systems and Methods for Multi-Stage Data Serialization in a Memory System
Thermocompression Bond Tips and Related Apparatus and Methods
Apparatuses Comprising Memory Cells, and Apparatuses Comprising Memory Arrays
Application:
62/527,564 →
Systems and Methods for Memory Cell Array Initialization
Memory Circuitry
Application:
62/533,205 →
Apparatuses and Methods for Memory Including Ferroelectric Memory Cells and Dielectric Memory Cells
Application:
62/532,205 →
Tri-Level Dram Sense Amplifer
Application:
62/490,904 →
Semiconductor Device Assembly with Surface-Mount Die Support Structures
Data Replication
Self-Reference Sensing for Memory Cells
Responding to Power Loss
Methods of Forming Semiconductor Device Structures, and Related Semiconductor Device Structures, Semiconductor Devices, and Electronic Systems
Apparatuses and Methods for Providing Constant Dqs-Dq Delay in a Memory Device
Patent:
10,026,462 →
Application:
15/596,988 →
Apparatuses and Methods for Detection Refresh Starvation of a Memory
Dual Mode Ferroelectric Memory Cell Operation
Apparatus and Methods for Testing Devices
Magnetic Memory Device with a Common Source having an Array of Openings, System, and Method of Fabrication
Plate Node Configurations and Operations for a Memory Array
Application:
62/504,299 →
Programming Enhancement in Self-Selecting Memory
Semiconductor Device Assemblies with Annular Interposers
Patent:
10,096,576 →
Application:
15/621,939 →
Arrays Of Memory Cells And Methods Of Forming An Array Of Elevationally-Outer-Tier Memory Cells And Elevationally-Inner-Tier Memory Cells
Method of Forming Semiconductor Device Including Tungsten Layer
Partially Written Block Treatment
Power Gate Circuits for Semiconductor Devices
Time-Based Access of a Memory Cell
Mixed Cross Point Memory
Refresh in Memory Based on a Set Margin
Memory Device with Dynamic Programming Calibration
Memory Device with Dynamic Program-Verify Voltage Calibration
Memory Device with Dynamic Processing Level Calibration
Apparatuses and Methods for Adaptive Spatial Diversity in a Mimo-Based System
Apparatuses and Methods for Controlling Word Lines and Sense Amplifiers
Multi-Phase Clock Generator
Self-Boost, Source Following, and Sample-and-Hold for Accessing Memory Cells
Memory System Including Data Obfuscation
FinFETs with Deposited Fin Bodies
Apparatuses and Methods for Automated Dynamic Word Line Start Voltage
Offset Cancellation for Latching in a Memory Device
Patent:
10,163,481 →
Application:
15/655,644 →
Apparatuses and Methods for Configurable Command and Data Input Circuits for Semiconductor Memories
Memory Plate Segmentation to Reduce Operating Power
Assemblies Which Include Wordlines Over Gate Electrodes
Memory Cells Having Resistors and Formation of the Same
Methods of Forming Staircase Structures
System for Optimizing Routing of Communication Between Devices and Resource Reallocation in a Network
Memory Arrays
Application:
62/502,999 →
Arrays Of Elevationally-Extending Strings Of Memory Cells And Methods Of Forming Memory Arrays
Patent:
9,985,049 →
Application:
15/581,762 →
Crypto-Ransomware Compromise Detection
Apparatuses and Methods to Control Memory Operations on Buffers
Semiconductor Constructions Having Fluorocarbon Material
Data Programming
Patent:
10,120,604 →
Application:
15/621,448 →
Memory Protocol with Command Priority
Memory Arrays
Application:
62/503,018 →
Secure Memory Arrangements
Application:
62/476,598 →
Adaptive Throttling
Semiconductor Constructions Comprising Dielectric Material
NAND Memory Arrays, and Devices Comprising Semiconductor Channel Material and Nitrogen
Controlling Memory Devices Using a Shared Channel
Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor
Application:
62/526,843 →
Apparatuses and Methods for Providing Additional Drive to Multilevel Signals Representing Data
Application:
62/534,436 →
Apparatuses with Compensator Lines Laid Out Along Wordlines and Spaced Apart from Wordlines by Dielectric, Compensator Lines Being Independently Controlled Relative to the Wordlines Providing Increased on-Current in Wordlines, Reduced Leakage in Coupled Transistors and Longer Retention Time in Coupled Memory Cells
Semiconductor Device Assemblies with Lids Including Circuit Elements
Patent:
10,090,282 →
Application:
15/621,955 →
Time-Based Access of a Memory Cell
Semiconductor Structures, Memory Cells and Devices Comprising Ferroelectric Materials, Systems Including Same, and Related Methods
Sense Amplifier Signal Boost
Methods and Systems for Averaging Impedance Calibration
Patent:
9,935,632 →
Application:
15/654,499 →
Apparatus Comprising Antifuse Cells
Interface Components
Patent:
10,140,222 →
Application:
15/642,906 →
Trench Isolation Interfaces
Integrated Computing Structures Formed on Silicon
Memory Cell Structures
Application:
15/641,475 →
Publication:
US US20190013387A1
Memory Cells Programmed via Multi-Mechanism Charge Transports
Patent:
10,153,039 →
Application:
15/641,597 →
Memory Cells Having an Access Gate and a Control Gate and Dielectric Stacks Above and Below the Access Gate
Patent:
10,153,381 →
Application:
15/641,521 →
Gated Diode Memory Cells
Memory Configurations
Patent:
10,153,348 →
Application:
15/641,628 →
Multifunctional Memory Cells
Methods of Forming Integrated Circuitry
Patent:
10,103,053 →
Application:
15/650,274 →
Half-Frequency Command Path
Patent:
10,063,234 →
Application:
15/649,145 →
Timing Based Arbitration Methods and Apparatuses for Calibrating Impedances of a Semiconductor Device
Data Output for High Frequency Domain
Patent:
10,157,648 →
Application:
15/652,986 →
Method and Apparatus for Precharge and Refresh Control
Wiring with External Terminal
Non-Volatile Memory System or Sub-System
Providing Power Information to Memory
Application:
62/506,977 →
Multifunctional Memory Cells
Memory Arrays
Finer Grain Dynamic Random Access Memory (Dram)
Application:
62/518,575 →
Unused Capability and Leveraging Storage for Managed Nand
Application:
62/521,939 →
Ufs 3.0 Improvements
Application:
62/529,910 →
Apparatuses and Methods for Refreshing Memory Cells of a Semiconductor Device
Semiconductor Device Suppressing Bti Deterioration
Semiconductor Device Having a Memory Cell and Method of Forming the Same
Method of Forming A Semiconductor Device Including A Pitch Multiplication
Device Having Multiple Switching Buffers for Data Paths Controlled Based on Io Configuration Modes
Semiconductor Device Having Error Correction Code (Ecc) Circuit
Semiconductor Device Including Fuse Circuit
Methods of Forming a Portion of a Memory Array Having a Conductor Having a Variable Concentration of Germanium
Command Line Output Redirection
Error Correction Code for Unidirectional Memory
Refresh Architecture and Algorithm for Non-Volatile Memories
Memory Device Having Address and Command Selectable Capabilities
Fast Programming Memory Device
High Speed, Parallel Configuration of Multiple Field Programmable Gate Arrays
Memory Programming Methods and Memory Systems
Memory Systems and Memory Programming Methods
Automatic Word Line Leakage Measurement Circuitry
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 3, 2017
From: SCHUBERT, MARTIN F.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042230/0859 →
Assignment of Assignor's Interest
May 12, 2017
From: SCHUBERT, MARTIN F.; ODNOBLYUDOV, VLADIMIR; XU, LIFANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042364/0782 →
Supplement No. 5 to Patent Security Agreement
Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
Assignment of Assignor's Interest
Apr 20, 2018
From: TUTTLE, JOHN R.
To: KEYSTONE TECHNOLOGY SOLUTIONS, LLC
Reel/Frame 045604/0013 →
Assignment of Assignor's Interest
Apr 20, 2018
From: KEYSTONE TECHNOLOGY SOLUTIONS, LLC
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045991/0801 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
Release of Security Interest
Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →