Memory arrays
In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.
1. A memory array, comprising:
a first group of series-coupled memory cells adjacent to a first semiconductor pillar, wherein memory cells of the first group of series-coupled memory cells wrap completely around the first semiconductor pillar;
a second group of series-coupled memory cells adjacent to a second semiconductor pillar, wherein memory cells of the second group of series-coupled memory cells wrap completely around the second semiconductor pillar; and
a data line between and coupled to the first semiconductor pillar and the second conductor pillar such that the first and the second semiconductor pillars extend in opposite directions from the data line;
wherein a memory cell of the first group of series-coupled memory cells and a memory cell of the second group of series-coupled memory cells each comprise:
a respective gate;
a respective first dielectric stack between a first portion of the respective gate and the semiconductor pillar, wherein the respective first dielectric stack is wrapped completely around the semiconductor pillar and is to store a charge; and
a respective second dielectric stack between a second portion of the respective gate and the semiconductor pillar, wherein a memory cell of the first group of series-coupled memory cells and a memory cell of the second group of series-coupled memory cells each comprise:
a respective gate;
a respective first dielectric stack between a first portion of the respective gate and
a respective semiconductor pillar of the first and second semiconductor pillars,
wherein the respective first dielectric stack is wrapped completely around the respective semiconductor pillar and is to store a charge; and
a respective second dielectric stack between a second portion of the respective gate and the respective semiconductor pillar, wherein the second dielectric stack is to store a charge and is wrapped completely around the respective semiconductor pillar such that the respective second dielectric stack is separated from the respective first dielectric stack along the respective semiconductor pillar.
2. The memory array of claim 1 , wherein the respective gate further comprises a respective third portion contiguous with the first portion of the respective gate and the second portion of the respective gate and that is between the respective first dielectric stack and the respective second dielectric stack.
3. The memory array of claim 1 , further further comprising a respective interface dielectric between a third portion of the respective gate and the respective semiconductor pillar.
4. The memory array of claim 3 , wherein the memory cell of the first group of series-coupled memory cells and the memory cell of the second group of series-coupled memory cells each comprise:
a respective first non-volatile portion, comprising the first portion of the respective gate and the respective first dielectric stack;
a respective fixed-threshold-voltage portion in series with the respective first non-volatile portion and comprising the third portion of the respective gate and the respective interface dielectric; and
a respective second non-volatile portion in series with the respective fixed-threshold-voltage portion and comprising the second portion of the respective gate and the respective second dielectric stack.
5. The memory array of claim 1 , wherein the first and second portions of the respective gate respectively wrap completely around the respective first dielectric stack and the respective second dielectric stack and are separated along the respective semiconductor pillar.
6. The memory array of claim 1 , wherein the respective first dielectric stack and the respective second dielectric stack each comprise:
a first storage dielectric;
a tunnel dielectric adjacent to the first storage dielectric;
a charge trap adjacent to the tunnel dielectric;
a second storage dielectric adjacent to the charge trap; and
a blocking dielectric adjacent to the second storage dielectric.
7. A memory array, comprising:
a first group of series-coupled memory cells adjacent to a first semiconductor pillar, wherein memory cells of the first group of series-coupled memory cells wrap completely around the first semiconductor pillar;
a second group of series-coupled memory cells adjacent to a second semiconductor pillar, wherein memory cells of the second group of series-coupled memory cells wrap completely around the second semiconductor pillar; and
a data line between and coupled to the first semiconductor pillar and the second conductor pillar such that the first and the second semiconductor pillars extend in opposite directions from the data line.
8. The memory array of claim 7 , wherein the data line is shared by the first group of series-coupled memory cells and the second group of series-coupled memory cells.
9. The memory array of claim 7 , further comprising a first select transistor to selectively couple the first group of series-coupled memory cells to the data line and a second select transistor to selectively couple the second group of series-coupled memory cells to the data line.
10. The memory array of claim 7 , wherein
a memory cell of the first group of series-coupled memory cells and a memory cell of the second group of series-coupled memory cells each comprise:
a first dielectric stack to store a charge;
a second dielectric stack to store a charge; and
a single gate coupled to both the first and second dielectric stacks;
the first dielectric stack and the second dielectric stack of the memory cell of the first group of series-coupled memory cells are respectively located at different locations along the first semiconductor pillar; and
the first dielectric stack and the second dielectric stack of the memory cell of the second group of series-coupled memory cells are respectively located at different locations along the second semiconductor pillar.
11. The memory array of claim 7 , wherein the first group of series-coupled memory cells is a mirror image of the second group of series-coupled memory cells.
12. The memory array of claim 7 , further comprising:
a source/drain in the first semiconductor pillar in direct physical contact with the data line; and
a source/drain in the second semiconductor pillar in direct physical contact with the data line.
13. The memory array of claim 7 , wherein the data line is a bit line.
14. The memory array of claim 7 , wherein the first semiconductor pillar is coupled to the second semiconductor pillar at the data line.