Semiconductor apparatus with multiple tiers, and methods
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
1. A method of forming a memory structure, comprising:
forming multiple vertically arranged tiers, each tier comprising an access line of a respective group of memory cells, each tier also including at least one of a source, a channel, and a drain of a respective peripheral transistor; and
forming multiple pillars comprising semiconductor material extending vertically through the multiple vertically arranged tiers, a first pillar of the multiple pillars comprising at least one of a source, a channel and a drain of each of multiple memory cells, and a second pillar of the multiple pillars comprising a gate of at least one peripheral transistor.
2. The method of claim 1 , wherein the first pillar comprises a first semiconductor material; and wherein the multiple vertically arranged tiers each comprise a second semiconductor material.
3. The method of claim 2 , wherein the multiple vertically arranged tiers each comprise the second semiconductor material in a first region, and further comprise a metal in a second region.
4. The method of claim 3 , wherein the at least one of a source, a channel, and a drain of a respective peripheral transistor is formed of the second semiconductor material in the first region, and wherein the access lines are formed of the metal in the second region.
5. The method of claim 2 , further comprising:
forming a slot through the tiers of the second semiconductor material to separate a first portion of the tiers of the second semiconductor material that includes a first group of memory cells from a second portion of the tiers of the second semiconductor material that includes a second group of memory cells.
6. The method of claim 5 , wherein the first pillar is a U-shaped pillar extending through respective memory cells of the first and second groups.
7. The method of claim 5 , further comprising:
forming a slot through the tiers of semiconductor material to separate a first portion of the tiers of semiconductor material including the portions of the memory cells from a second portion of the tiers of the semiconductor material including the portions of the peripheral transistors;
forming the first portion of the tiers of semiconductor material into a first staircase configuration; and
forming the second portion of the tiers of semiconductor material into a second staircase configuration.
8. The method of claim 5 , further comprising:
forming a slot through the tiers of semiconductor material to separate a first portion of the tiers of semiconductor material including the portions of the memory cells from a second portion of the tiers of the semiconductor material including the portions of the decoder transistors; and
forming a plurality of pillars of semiconductor material to extend through a plurality of the tiers of semiconductor material, each pillar of semiconductor material comprising either a source, a channel and/or a drain of at least one of the memory cells, or a gate of at least one of the decoder transistors.
9. The method of claim 5 , further comprising coupling a respective one of the portions of a memory cell to a respective one of the portions of a peripheral transistor.
10. The method of claim 5 , wherein forming a plurality of tiers of a semiconductor material comprises:
forming a plurality of tiers of n-type polysilicon; and
forming silicon dioxide between the tiers of n-type polysilicon.
11. The method of claim 1 , wherein each access line is formed coupled to one of the source and the drain of a respective peripheral transistor of the multiple peripheral transistors.
12. A method comprising:
forming multiple vertically-spaced tiers of a semiconductor material;
forming a respective portion of respective memory cells in at least two of the tiers of the semiconductor material, including forming a respective access line of the respective memory cells in the respective tier of semiconductor material; and
forming a respective portion of respective peripheral transistors in at least two of the tiers of the semiconductor material, including forming at least one of a respective source, channel and drain of the peripheral transistor in each tier of semiconductor material.
13. The method of claim 12 , wherein the peripheral transistor formed with at least one of a respective source, channel and drain in each tier of two tiers of a semiconductor material is a decoder transistor.