Semiconductor apparatus with multiple tiers, and methods
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
1. An apparatus comprising:
multiple tiers of a first semiconductor material, each tier comprising an access line of a respective memory cell, each of such tiers also including at least one of a source, a channel and a drain of a respective peripheral transistor; and
multiple pillars of a second semiconductor material extending through the tiers of the first semiconductor material, a first pillar of the multiple pillars comprising at least one of a source, a channel and a drain of each of multiple memory cells, and a second pillar of the multiple pillars comprising a gate of at least one of the peripheral transistors.
2. The apparatus of claim 1 , wherein each access line is coupled to one of the source and the drain of a respective one of the peripheral transistor of the peripheral transistors.
3. The apparatus of claim 1 , wherein:
the first semiconductor material comprises n-type silicon; and
the second semiconductor material comprises polysilicon.
4. The apparatus of claim 1 , wherein each of the peripheral transistors comprises a plurality of gates.
5. The apparatus of claim 1 , further comprising:
a slot through the tiers of the first semiconductor material that separates a first portion of the tiers of the first semiconductor material that includes a first group of the memory cells from a second portion of the tiers of the first semiconductor material that includes a second group of the memory cells,
wherein the first pillar is a U-shaped pillar extending through respective memory cells of the first and second groups.
6. An apparatus comprising:
a plurality of vertically disposed tiers, comprising,
in a first portion, the tiers formed of a first semiconductor material, each tier of the first semiconductor material comprising at the least one of a source, a channel and a drain of a respective peripheral transistor;
in a second portion, the tiers formed of metal, each tier of metal comprising an access line of a respective memory cell, each portion of a tier former of metal coupled to a respective portion of the tier formed of semiconductor material.
7. The apparatus of claim 6 , further comprising multiple first pillars of a second semiconductor material extending through the tiers of metal of the second portion, each of the first pillars comprising at least one of a source, a channel and a drain of at least one of the memory cells.
8. The apparatus of claim 6 , further comprising multiple second pillars of a semiconductor material extending through the tiers of the first semiconductor material of the first portion, each of the second pillars comprising a gate of at least one of the peripheral transistors.
9. The apparatus of claim 6 , wherein:
the metal is selected from the group consisting of one or more of titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and Tungsten (W), in any combination; and
the first semiconductor material comprises polysilicon.
10. The apparatus of claim 6 , wherein each of the peripheral transistors comprises a decoder transistor.
11. The apparatus of claim 6 , wherein the peripheral transistor comprises a decoder transistor.
12. The apparatus of claim 6 , further comprising a slot through the plurality of tiers of the first semiconductor material to separate portions of memory cells and portions of peripheral transistors.