Error detection code hold pattern synchronization
A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.
1. A memory system, comprising:
a memory device;
a command clock (CK_t clock) configured to provide a first clock signal at a first frequency;
a data path clock (WCK_t clock) configured to provide a second clock signal at a second frequency different than the first frequency;
data path circuitry synchronized with the WCK_t clock, wherein the data path circuitry is configured to provide an error detection code (EDC) hold pattern during an idle state; and
EDC hold pattern synchronization logic configured to synchronize a start of transmission of the EDC hold pattern synchronous to the CK_t clock, wherein the EDC hold pattern synchronization logic comprises a first data flip flop timed to the CK_t clock, the first data flip flop configured to provide an EDC hold reset signal to EDC hold pattern generation circuitry.
2. The memory system of claim 1 , wherein the EDC hold pattern synchronization logic is configured to synchronize the start of transmission of the EDC hold pattern during initialization of the memory device.
3. The memory system of claim 1 , wherein the EDC hold pattern synchronization logic is configured to synchronize the start of transmission of the EDC hold pattern by:
de-asserting an asserted EDC hold reset signal synchronous to a rising edge of the CK_t clock.
4. The memory system of claim 3 , wherein the data path circuitry is configured to trigger provision of the EDC hold pattern when the EDC hold reset signal is de-asserted.
5. The memory system of claim 1 , comprising a memory controller configured to selectively enable provision, via EDC pads of the memory, between:
calculated error correction checksum data; and
the EDC hold pattern.
6. The memory system of claim 1 , wherein the memory device comprises double data rate type five x synchronous graphics random-access (GDRR5X) memory.
7. The memory system of claim 1 , wherein the memory device comprises double data rate type six synchronous graphics random-access (GDRR6) memory.
8. The memory system of claim 1 , wherein the EDC hold pattern comprises 4 bits of data.
9. An integrated circuit, comprising:
a memory controller configured to coordinate data transmission of a memory device;
error detection code (EDC) path circuits, timed to a data path clock (WCK_t clock) that provides a first clock signal at a first frequency, wherein the EDC path circuits are configured to provide error correction checksum data when an error detection mode is active;
EDC hold pattern generation circuitry configured to provide an EDC hold pattern when a standby mode is active; and
EDC hold pattern synchronization logic configured to synchronize a start of transmission of the EDC hold pattern with a command clock (CK_t clock) configured to provide a second clock signal at a second frequency, wherein the EDC hold pattern synchronization logic comprises a first data flip flop timed to the CK_t clock, the first data flip flop configured to provide an EDC hold reset signal to the EDC hold pattern generation circuitry.
10. The integrated circuit of claim 9 , comprising:
a multiplexor that is configured to receive:
the error correction checksum data from the ECD path circuits as a first input;
the EDC hold pattern from the EDC hold pattern generation circuitry as a second input; and
a data selector signal from the memory controller, the data selector signal based upon whether the error detection mode is active or the standby mode is active;
wherein the multiplexor that is configured to selectively provide either the error correction checksum data or the EDC hold pattern, based upon the data selector signal.
11. The integrated circuit of claim 10 , wherein the EDC hold pattern synchronization logic is configured to synchronize the start of transmission of the EDC hold pattern with a falling edge of the EDC hold reset signal.
12. The integrated circuit of claim 10 , wherein the EDC hold pattern synchronization logic comprises a second data flip flop timed to the WCK_t clock that provides the EDC hold pattern, based upon an inversion of the EDC hold reset signal.
13. The integrated circuit of claim 9 , comprising the memory device, wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.