FinFETs with deposited fin bodies
Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.
1. A method of fabricating a fin field effect transistor, the method comprising:
forming a structure extending from a base on a substrate, including forming the structure having a first dielectric with a dielectric surface extending from the base, the structure having a first conductive region within the first dielectric, with the first conductive region formed within the first dielectric by forming the first conductive region on an inner portion of the first dielectric and forming an outer portion of the first dielectric on the first conductive region:
depositing material on the dielectric surface, forming a fin body of a fin field effect transistor;
forming a second dielectric contacting the fin body on a surface of the fin body opposite the dielectric surface of the first dielectric;
forming a second conductive region on the second dielectric, the second conductive region separated from the fin body by the second dielectric; and
forming a doped region to the fin body, wherein forming the structure extending from the base on the substrate includes forming the base by:
forming a conductive region on the substrate, the conductive region formed as a digitline for the device; and
forming a doped region on and contacting the digitline such that the structure is formed extending from the doped region.
2. The method of claim 1 , wherein forming the structure extending from the base on the substrate includes:
forming the first conductive region extending from above the base to a level less than a top surface of the structure; and
forming the outer portion of the first dielectric as part of a first region adjacent to and contacting the first conductive region.
3. The method of claim 2 , wherein the first dielectric and the first region have a substantially same dielectric oxide composition.
4. The method of claim 1 , wherein depositing material on the dielectric surface includes depositing a polycrystalline silicon material.
5. The method of claim 1 , wherein forming the doped region to the fin body includes forming the doped region on a portion of the deposited material that is substantially perpendicular to the formed fin body.
6. A method of fabricating a memory device, the method comprising:
forming multiple structures extending from a base on a substrate, including forming each structure having a first conductive region and a second conductive region embedded in a first dielectric and separated from each other by the first dielectric, each structure having a first dielectric surface extending from the base and extending from the first conductive region in the structure and a second dielectric surface extending from the base and extending from the second conductive region in the structure;
depositing material on the first and second dielectric surfaces of each structure, forming multiple fin bodies for multiple fin field effect transistors;
forming a second dielectric between each structure of the multiple structures contacting the deposited material of each structure of the multiple structures, each second dielectric including a third conductive region and a fourth conductive region embedded in the second dielectric between two structures of the multiple structures, the third conductive region and the fourth conductive region separated from each other by the second dielectric;
forming a doped region to the deposited material of each structure, the doped region formed on the multiple structures and second dielectric opposite the base;
removing portions of the doped region, the deposited material for the fin bodies, and the second dielectric, to define the multiple fin field effect transistors, each fin field effect transistor having two gates; and
coupling the fin field effect transistors to charge storage elements.
7. The method of claim 6 , wherein forming multiple structures extending from the base includes forming the base along a digitline line for the device and the method includes patterning in a direction perpendicular to the digitline line forming an array of cells coupled to multiple digitlines, each digitline physically and electrically separate from each other.
8. The method of claim 7 , wherein depositing the material forming multiple fin bodies for multiple fin field effect transistors includes depositing the material for a 48 nm array pitch.
9. The method of claim 6 , wherein prior to depositing material on the first and second dielectric surfaces of each structure, the method includes forming a thin polycrystalline semiconductor region on the first and second dielectric surfaces of each structure; and depositing material on the first and second dielectric surfaces of each structure includes depositing the material on the thin polycrystalline semiconductor region, the thin polycrystalline semiconductor region being thin relative to the deposited material.
10. The method of claim 6 , wherein the method includes forming the first, second, third, and fourth conductive regions as titanium nitride gates.
11. The method of claim 6 , wherein depositing material forming multiple fin bodies includes depositing the material by chemical vapor deposition or by atomic layer deposition.
12. The method of claim 6 , wherein depositing material forming multiple fin bodies includes forming each fin body to have a thickness in the range of 10 angstroms to 100 angstroms.
13. The method of claim 6 , wherein depositing material on the first and second dielectric surfaces of each structure includes depositing the material on a doped region formed on and contacting a conductive region formed on the substrate, the conductive region formed as a digitline for the device.
14. The method of claim 13 , wherein forming the multiple fin field effect transistors includes forming the multiple fin field effect transistors material deposited on the doped region formed on and contacting the conductive region.
15. The method of claim 6 , wherein coupling the fin field effect transistors to charge storage elements includes forming a capacitor coupled to portion of the doped region, formed on the multiple structures and second dielectric opposite the base, remaining after removing a portion of the doped region.
16. A device comprising:
a digitline;
a first dielectric;
a deposited fin body extending from a first doped region contacting the digitline to a second doped region distal from the digitline, the deposited fin body deposited on the first dielectric;
a first gate separated from the deposited fin body by the first dielectric;
a second dielectric adjacent the deposited fin body on a side of the deposited fin body opposite the first dielectric; and
a second gate separated from the deposited fin body by the second dielectric and substantially parallel to the first gate.
17. The device of claim 16 , wherein the deposited fin body has a thickness in the range of 10 angstroms to 100 angstroms.
18. The device of claim 16 , wherein the first doped region contacting the digitline, the first dielectric, the first gate, the second dielectric, the second gate, and the fin body are structured as an access transistor in the device.
19. The device of claim 16 , wherein the first doped region contacting the digitline includes material of the fin body doped to a higher level than the material of the fin body.
20. A device comprising:
a number of digitlines;
multiple fin field effect transistors disposed on each digitline, each fin field effect transistor on each digitline including
a first dielectric;
a deposited fin body extending from a first doped region contacting the digitline to a second doped region distal from the digitline, the deposited fin body deposited on the first dielectric;
a first gate separated from the deposited fin body by the first dielectric;
a second dielectric adjacent the deposited fin body on a side of the deposited fin body opposite the first dielectric; and
a second gate separated from the deposited fin body by the second dielectric and substantially parallel to the first gate; and
multiple access lines, each access line coupled to one the first gate or the second gate of multiple fin field effect transistors disposed along the access line.
21. The device of claim 20 , wherein the multiple fin field effect transistors disposed on each digitline of the number of digitlines is structured having a 48 nm array pitch.
22. The device of claim 20 , wherein the deposited fin body includes a polycrystalline semiconductor material.
23. The device of claim 22 , wherein the deposited fin bodies of directly adjacent fin field effect transistors disposed on the same digitline are coupled to each other by a region disposed on and contacting the first doped region contacting the digitline, the region composed of the polycrystalline semiconductor material.
24. The device of claim 20 , wherein the first gate of a fin field effect transistor of the multiple fin field effect transistors is separated from the second gate of a directly adjacent fin field effect transistor disposed on the same digitline by an oxide.
25. A wafer comprising:
multiple dice, each die of the multiple dice including
a digitline;
a fin field effect transistor coupled to the digitline, the fin field effect transistor having
a first dielectric;
a deposited fin body extending from a first doped region contacting the digitline to a second doped region distal from the digitline, the deposited fin body deposited on the first dielectric;
a first gate separated from the deposited fin body by the first dielectric;
a second dielectric adjacent the deposited fin body on a side of the deposited fin body opposite the first dielectric; and
a second gate separated from the deposited fin body by the second dielectric and substantially parallel to the first gate.
26. The wafer of claim 25 , wherein each die includes a number of digitlines with multiple fin field effect transistors disposed on each digitline.
27. The wafer of claim 26 , wherein the multiple fin field effect transistors disposed on each digitline of the number of digitlines is structured having a 48 nm array pitch.
28. The wafer of claim 25 , wherein the deposited fin body includes multiple material compositions.
29. The wafer of claim 25 , wherein the digitline in each die is coupled to a sense amplifier in each die.