IP Library Granted Patent US 10,140,222
Granted Patent B1
US 10,140,222 · App. 15/642,906 · Granted Nov 27, 2018

Interface components

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Quick Facts
Patent No.
US 10,140,222
App. No.
15/642,906
Granted
Nov 27, 2018
Kind
B1
Abstract

In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Claims (8)

1. An apparatus, comprising:

a controller; and

a plurality of interface components, wherein the controller communicates with respective ones of the plurality of interface components respectively over respective ones of a plurality of first channels;

wherein a first interface component of the plurality of interface components communicates with a first plurality of memory devices over a first one of a plurality of second channels and a second plurality of memory devices over a second one of the plurality of second channels; and

wherein a second interface component is coupled in series with the first interface component, wherein the second interface component communicates with a third plurality of memory devices over a first one of a plurality of third channels and a fourth plurality of memory devices over a second one of the plurality of third channels.

2. The apparatus of claim 1 , wherein the first interface component is to determine whether a packet from the controller is intended for the first interface component.

3. The apparatus of claim 2 , wherein the first interface component is to act on the packet in response to determining that the packet is intended for first interface component and to send the packet to second interface component in response to determining that the packet is not intended for the first interface component.

4. The apparatus of claim 1 , wherein the first interface component is to pass a signal from the second interface component to the controller.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2017
From: ROWLEY, MATTHEW D.; CASTRO, PETER R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042924/0476 →