Gated diode memory cells
Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.
1. A nonvolatile memory cell, comprising:
an access device coupled to a first access line and a second access line, the first access line coupled to a substrate and the second access line coupled to a gated diode structure formed within the substrate, wherein the gated diode comprises:
a n-type silicon material coupled to an intrinsic region; and
a first p-type silicon material coupled to the intrinsic region, wherein the access device further comprises:
a shallow trench isolation (STI) region coupled to the first p-type silicon region; and
a second p-type silicon material coupled to the STI region, and
an ohmic contact coupled to the first p-type silicon material, the STI region, and the second p-type material.
2. The memory cell of claim 1 , further comprising a conductive line coupled to a gate of the gated diode.
3. The memory cell of claim 1 , wherein the gated diode is formed in a direction substantially orthogonal to the plurality of access lines and the plurality of data lines.
4. The memory cell of claim 1 , wherein the gated diode is formed in a direction substantially parallel to the plurality of access lines and the plurality of data lines.
5. The memory cell of claim 1 , wherein the gated diode is configured such that a cycle time for the memory cell is less than one nanosecond.
6. The memory cell of claim 1 , wherein the gated diode is a three-terminal diode.
7. An apparatus, comprising:
a cross-point memory array comprising a plurality of data lines and access lines coupled to a substrate, wherein the data lines and access lines are substantially orthogonal to each other;
a gated diode within the substrate and disposed between a first access line and a second access line among the plurality of access lines, wherein the gated diode comprises:
a n-type silicon material coupled to an intrinsic region; and
a first p-type silicon material coupled to the intrinsic region, and wherein the cross-point memory array further comprises:
a shallow trench isolation (STI) region coupled to the first p-type silicon region;
a second p-type silicon material coupled to the STI region; and
an ohmic contact coupled to the first p-type silicon material, the STI region, and the second p-type material.
8. The apparatus of claim 7 , wherein at least one of the n-type silicon material, the intrinsic region material, and the first p-type silicon material have a dielectric constant greater than 20.
9. The apparatus of claim 7 , further comprising a controller configured to cause a memory cell associated with the cross-point memory array to be programmed using a voltage that is substantially equal to 1.5 volts or less.
10. The apparatus of claim 7 , wherein:
the n-type silicon material comprises a direct tunnel layer;
the intrinsic region comprises a deep-offset trapping layer; and
the first p-type silicon material comprises a blocking layer.
11. The apparatus of claim 7 , wherein:
the n-type silicon material comprises Lanthanum Oxide or Hafnium Oxide;
the intrinsic region is Gallium Nitride; and
the first p-type silicon material comprises Lanthanum Oxide or Hafnium Lanthanum Oxide Nitride.
12. A method of forming a memory cell, comprising:
forming a semiconductor substrate having a source region and a drain region;
forming an access device on the semiconductor substrate;
forming a gated diode structure within the semiconductor substrate, wherein the gated diode structure comprises:
a n-type silicon material coupled to an intrinsic region; and
a first p-type silicon material coupled to the intrinsic region;
forming a shallow trench isolation (STI) region coupled to the first p-type silicon material;
forming a second p-type silicon material coupled to the STI region; and
forming an ohmic contact coupled to the first p-type silicon material, the STI region, and the second p-type silicon material.
13. The method of claim 12 , wherein the gate stack structure is formed to have an equivalent oxide thickness substantially equal to 2 nanometers.
14. The method of claim 12 , wherein the gate stack structure is formed to have an equivalent oxide thickness substantially equal to 2.3 nanometers.
15. The method of claim 12 , wherein the gate stack structure is formed to have a barrier energy against silicon substantially equal to 2 electron-volts.
16. The method of claim 12 , wherein the gate stack structure is formed to have a leakage rate at least five orders of magnitude lower than a leakage rate associated with silicon dioxide.
17. The method of claim 12 , wherein forming the gate stack structure comprises:
forming a direct tunnel material comprising Lanthanum Oxide and having a thickness substantially equal to 2 nanometers (nm);
forming a deep-offset trapping material comprising Gallium nitride and having a thickness substantially equal to 3 nm; and
forming a blocking material comprising Lanthanum Oxide and having a thickness substantially equal to 5 nm.
18. The method of claim 12 , wherein forming the gate stack structure comprises:
forming a direct tunnel material comprising Hafnium oxide and having a thickness substantially equal to 1.5 nanometers (nm);
forming a deep-offset trapping material comprising Gallium nitride and having a thickness substantially equal to 3 nm; and
forming a blocking material comprising Hafnium Lanthanum Oxide nitride and having a thickness substantially equal to 4 nm.