Apparatuses and methods for parity determination using sensing circuitry
The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
1. An apparatus, comprising:
an array of memory cells;
a controller configured to operate sensing circuitry to:
perform a first XOR operation on a data value stored in a first memory cell and a data value stored in a second memory cell of a number of memory cells coupled to a sense line of the array that results in a first resultant value; and
perform a second XOR operation on the first resultant value and a data value stored in a third memory cell of the number of memory cells resulting in a second resultant value, wherein the second resultant value protects the data stored in the first memory cell, the data stored in the second memory cell, and the data stored in the third memory cell.
2. The apparatus of claim 1 , wherein the first XOR operation is performed without enabling a decode line coupled to the sensing circuitry.
3. The apparatus of claim 1 , wherein the second XOR operation is performed without enabling a decode line coupled to the sensing circuitry.
4. The apparatus of claim 1 , comprising a processing resource external to the sensing circuitry.
5. The apparatus of claim 4 , wherein the second resultant value is sent to the processing resource.
6. The apparatus of claim 1 , wherein the controller is configured to operate the sensing circuitry to perform a number of subsequent XOR operations on resultant values from prior XOR operations and data values stored in remaining memory cells of the array without enabling a decode line.
7. The apparatus of claim 1 , wherein the controller is configured to operate the sensing circuitry to repeat performance of a plurality of XOR operations on resultant values from prior XOR operations and data values stored in remaining memory cells of the array until a respective XOR operation has been performed on each of the number of memory cells coupled to the sense line.
8. The apparatus of claim 7 , wherein an XOR output value from the plurality of XOR operations is a parity value corresponding to the data values stored in the number of memory cells; and
the XOR output value is sent to a processing resource external to the sensing circuitry.
9. The apparatus of claim 8 , wherein the controller is further configured to cause a rollback to a prior state of the data values stored in the number of memory cells when the XOR output value indicates an error is detected.
10. An apparatus, comprising:
an array of memory cells comprising a plurality of sense lines each coupled to corresponding sensing circuitry and having a number of memory cells coupled thereto, wherein each of the number of memory cells are coupled to one of a respective number of access lines; and
a controller configured to operate the sensing circuitry to:
perform, on a sense line by sense line basis, a number of exclusive OR (XOR) operations on data values stored in the number of memory cells coupled to a particular sense line to determine parity values corresponding to the data stored in the memory cells of the respective plurality of sense lines, wherein the parity values protect the respective data values stored in the number of memory cells.
11. The apparatus of claim 10 , wherein the number of XOR operations are performed without transferring data from the array via an input/output (I/O) line.
12. The apparatus of claim 10 , wherein the determined parity values are sent to a processing resource that is external to the sensing circuitry.
13. The apparatus of claim 10 , wherein the sensing circuitry corresponding to the respective plurality of sense lines each comprises a sense amplifier and a compute component, and wherein the plurality of sense lines each have a corresponding complementary sense line also coupled to the corresponding sense amplifier and to the corresponding compute component.
14. The apparatus of claim 10 , wherein:
the controller is further configured to store the determined parity values in additional memory cells couples to the respective sense lines; and
the additional memory cells are coupled to a same access line.
15. The apparatus of claim 10 , wherein the controller is configured to cause the sensing circuitry to:
perform a first AND operation on the data values;
perform an invert operation on the data values;
perform an OR operation on the data values; and
perform a second AND operation on a result from the first AND operation and a result from the OR operation.
16. An apparatus, comprising:
an array of memory cells configured to store data in each of a number of memory cells coupled to a sense line;
a controller configured to operate sensing circuitry to:
perform an XOR operation on the data stored in each of the number of memory cells without activating a decode signal, wherein performing the XOR operation includes:
performing a NAND operation on data values stored in a first memory cell and a second memory cell coupled to the sense line;
performing an OR operation on the data values; and
performing an AND operation on a result of the NAND operation and a result of the OR operation; and
determine a parity value corresponding to the data based on a result of the AND operation, wherein the parity value protects the data stored in each of the number of memory cells coupled to the sense line.
17. The apparatus of claim 16 , wherein the controller is further configured to determine a parity value corresponding to the data based on a result of the AND operation.
18. The apparatus of claim 17 , comprising a processing resource external to the sensing circuitry, wherein the controller is further configured to send the parity value to the processing resource.
19. The apparatus of claim 16 , wherein the NAND operation performed on the data values stored in the first memory cell and the second memory cell comprises:
loading a compute component coupled to the sense line with the data value stored in the first memory cell; and
enabling an access line to which the second memory cell is coupled and a control line to which a pass transistor is coupled.
20. The apparatus of claim 19 , wherein the controller is further configured to operate the sensing circuitry to invert an output value resulting from enabling the access line to which the second memory cell is coupled and the particular control signal to which the pass transistor is coupled.