Methods for performing processing-in-memory operations, and related systems
Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.
1. A system, comprising:
logic configured to:
multiply each bit of a number of bits from an array by a first bit of an input vector from a sequencer to generate a first row of bits;
multiply each bit of the number of bits by one or more additional bits of the input vector to generate one or more additional rows of bits; and
generate an output row of bits based on at least the first row of bits and the one or more additional rows of bits.
2. The system of claim 1 , the logic comprising one or more fused-multiply-add (FMA) units to generate the one or more additional rows of bits.
3. The system of claim 1 , the logic comprising:
the sequencer configured to receive the input vector; and
a sense amplifier configured to receive the number of bits in a bit-parallel manner.
4. The system of claim 1 , wherein the logic is further configured to:
multiply each bit of a second number of bits from the array by a first bit of a second input vector from the sequencer to generate a third row of bits;
multiply each bit of the second number of bits by one or more additional bits of the second input vector to generate at least one additional row of bits;
generate an additional output row of bits based on at least the third row of bits and the at least one additional row of bits; and
sum, along columns, the output row and the additional output row to generate a row of an output matrix.
5. The system of claim 1 , further comprising a memory device including the logic, wherein the memory device includes the sequencer.
6. The system of claim 1 , further comprising a memory device including the logic, wherein the sequencer is external to the memory device.
7. The system of claim 1 , wherein the logic comprises a number of groups of sense amplifiers, each group of sense amplifiers of the number of groups of sense amplifiers configured to receive a tile associated with a portion of the number of bits.
8. The system of claim 1 , wherein the logic is configured to sum, along associated bit positions, the first row of bits and the one or more additional rows of bits.
9. The system of claim 1 , further comprising:
at least one input device;
at least one output device;
at least one processor device coupled to the input device and the output device; and
at least one memory device coupled to the at least one processor device and comprising the logic.
10. A method, comprising:
multiplying each bit of a number of bits from an array by a first bit of an operand from a sequencer to generate a first row of bits;
multiplying each bit of the number of bits by one or more additional bits of the operand to generate one or more additional rows of bits; and
generating an output row based on at least the first row of bits and the one or more additional rows of bits.
11. The method of claim 10 , further comprising:
multiplying each bit of a second number of bits from the array by a second bit of the operand to generate a third row of bits;
multiplying each bit of the second number of bits by at least one additional bit of the operand to generate at least one additional row of bits; and
generating another output row based on at least the third row of bits and the at least one additional rows of bits.
12. The method of claim 10 , further comprising loading a plurality of bits of the operand from a second array into the sequencer.
13. The method of claim 10 , further comprising loading the number of bits from the array into a second array.
14. A memory system, comprising:
at least one memory array; and
logic coupled to the at least one memory array and configured to:
multiply each bit of a group of bits by each bit of an input to generate a number of rows, each row of the number of rows including a number of columns and each row of each of the number of rows shifted at least one column position relative to an adjacent row within the number of rows; and
generate an output row based on the number of rows.
15. The memory system of claim 14 , wherein the logic is configured to sum bits across columns within the number of rows to generate the output row.
16. The memory system of claim 14 , the logic further configured to:
multiply each bit of a second group of bits by each bit of the input to generate a number of additional rows, each row of the number of additional rows including a number of additional columns and each row of each of the number of additional rows shifted at least one column position relative to an adjacent row within the number of additional rows; and
generate an additional output row based on the number of additional rows.
17. The memory system of claim 16 , wherein the logic is configured to sum bits across columns within the number of additional rows to generate the additional output row.
18. The memory system of claim 14 , the logic further configured to receive the group of bits from a memory array of the at least one memory array, wherein each bit of the group of bits is received at the logic substantially simultaneously.
19. The memory system of claim 14 , wherein the logic comprises a sequencer including the input.
20. The memory system of claim 14 , wherein the logic comprises a sense amplifier configured to receive the group of bits in a bit-parallel manner.