Memristor arrays in crossbars

1. A memory cell, comprising:

a plurality of row lines;

a plurality of column lines, wherein the plurality of row lines and the plurality of column lines intersect to form a 2×2 array;

a plurality of memristors, wherein a memristor is coupled to each unique combination of a row line and a column line in the 2×2 array;

an input line coupled to a first row of memristors;

an inverter coupled to the input line; and

an inverted input line from the inverter coupled to the second row of memristors.

2. The memory cell of claim 1 , wherein the plurality of row lines comprise a selector coupled to each one of the plurality of memristors to program a value of each one of the plurality of memristors.

3. The memory cell of claim 1 , wherein one of the plurality of column lines comprise a bit line coupled to memristors in a first column of the 2×2 array, wherein the bit line is to set a value of the memristors in the first column of the 2×2 array.

4. The memory cell of claim 1 , wherein one of the plurality of column lines comprise a bit line bar coupled to memristors in a second column of the 2×2 array, wherein the bit line bar is to set a value of the memristors in the second column of the 2×2 array.

5. The memory cell of claim 1 , wherein the plurality of memristors comprises four memristors, wherein a first memristor is in a first row adjacent to a second memristor and wherein a third memristor is in a first column with the first memristor and in a second row adjacent to a fourth memristor that is in a second column with second memristor.

6. The memory cell of claim 5 , wherein the first memristor and the fourth memristor have the same value and the second memristor and the third memristor have the same value.

7. The memory cell of claim 1 , further comprising:

a current output from a first column of the 2×2 array;

a current output from a second column of the 2×2 array; and

a comparator coupled to the current output from the first column and the current output from the second column.

8. The memory cell of claim 1 , wherein the input line and the inverted input line are to represent bipolar values using positive values.

9. A crossbar, comprising:

a plurality of row lines;

a plurality of column lines, wherein the plurality of row lines and the plurality of column lines intersect to form a matrix of memory cells;

a plurality of memory cells, wherein each memory cell is coupled to each unique combination of a row line and a column line in the matrix, wherein each memory cell comprises a 2×2 array of memristors;

an input line coupled to each first row of memristors in the 2×2 array of memristors of the plurality of memory cells in the matrix;

an inverter coupled to the input line; and

an inverted input line coupled to a second row of memristors in the 2×2 array of memristors of the plurality of memory cells in the matrix.

10. The crossbar of claim 9 , wherein plurality of row lines comprise a selector coupled to each one of the memristors of each one of the plurality of memory cells.

11. The crossbar of claim 9 , wherein each one of the plurality of memory cells is programmed to a value of a weight matrix.

12. The crossbar of claim 11 , wherein the 2×2 array of memristors for each one of the plurality of memory cells is programmed to a value of 0 or a positive value to represent positive and negative input values.

13. The crossbar of claim 11 , wherein the weight matrix comprises a combination of positive weight values and negative weight values.

14. The crossbar of claim 9 , further comprising:

for each column of memory cells of the plurality of memory cells, a current output from a first column of each one of the 2×2 array of memristors of the memory cells in a respective column;

a current output from a second column of each one of the 2×2 array of memristors of the memory cells in the respective column; and

a comparator coupled to the current output from the first column and the current output from the second column for each column of memory cells.

15. A circuit, comprising:

a bipolar processing memory crossbar array to compute analog multiplications of a bipolar input vector;

an analog-to-digital converter (ADC) to generate digital results based on analog results computed by the bipolar processing memory crossbar array; and

a controller to generate an output based on the digital results and to control a voltage provided to the bipolar processing memory crossbar array.

16. The circuit of claim 15 , wherein the bipolar processing memory crossbar array comprises:

a plurality of row lines;

a plurality of column lines, wherein the plurality of row lines and the plurality of column lines intersect to form a matrix of memory cells; and

a plurality of memory cells, wherein each memory cell is coupled to each unique combination of a row line and a column line in the matrix.

17. The circuit of claim 16 , wherein each one off the plurality of memory cells comprises a 2×2 array of memristors.

18. The circuit of claim 17 , further comprising:

an input line coupled to each first row of memristors in the 2×2 array of memristors of the plurality of memory cells in the matrix;

an inverter coupled to the input line; and

an inverted input line coupled to a second row of memristors in the 2×2 array of memristors of the plurality of memory cells in the matrix.

19. The circuit of claim 15 , wherein bipolar input vector comprises a combination of positive and negative values that are represented as positive values.

20. The circuit of claim 19 , wherein a single bit value is represented as a two bit complementary value.