Granted Patent B2

US 10,430,210 · App. 15/534,978 · Granted Oct 1, 2019

Abstract

Claims (14)

1. A system, comprising:

a processor;

a direct memory access (DMA) controller coupled to the processor;

a buffer coupled to the DMA controller and configured to be accessed by the DMA controller, wherein the DMA controller performs a DMA transfer with a state machine engine comprising the buffer and configurable elements configured to analyze the at least a portion of a data stream and to selectively output a result of the analysis, wherein the buffer is configured to store at least one of an instruction or a data related to the data stream and is used for the DMA transfer; and

a second state machine engine comprising a second buffer, wherein the first state machine engine and the second state machine engine are configured to provide a respective count of the number of bytes in their respective buffer to the DMA controller as byte counts, wherein the DMA controller is configured to read the byte counts, determine the greatest number of bytes contained in any of the buffers of the first state machine and the second state machine as a greatest number of bytes value, round the greatest number of bytes value up to a nearest 8-byte burst boundary as a final number of bytes value, and set the DMA operation to read that final number of bytes value from the buffers of the first state machine engine and the second state machine engine.

2. The system of claim 1 , comprising the state machine engine, wherein the state machine engine comprises:

a first finite state machine lattice comprising the configurable elements; and

a second finite state machine lattice, wherein the second finite state machine lattice corresponds to a second set of configurable elements of the state machine engine configured to analyze at least a second portion of a data stream and to selectively output the result of the analysis.

3. The system of claim 2 , wherein the buffer includes an input buffer configured to store the at least a portion of a data stream to be analyzed by the state machine engine and the at least a second portion of a data stream to be analyzed by the state machine engine, wherein the state machine engine is configured to accept writes to a fixed address on a DDR bus and place the at least a portion of a data stream into a proper location in the input buffer.

4. The system of claim 3 , wherein the state machine engine is configured to accept writes to a second fixed address on the DDR bus and place at least a second portion of a data stream into a second proper location in the input buffer, wherein the first proper location corresponds to the first finite state machine lattice of the state machine engine, wherein the second proper location corresponds to the second finite state machine lattice of the state machine engine.

5. The system of claim 2 , wherein the buffer includes an input buffer configured to be divided into pieces that correspond to the first finite state machine lattice and the second finite state machine lattice, respectively.

6. The system of claim 5 , wherein the input buffer is configured to store the at least a portion of a data stream in a first piece of the input buffer and to store the at least a second portion of a data stream in a second piece of the input buffer.

7. The system of claim 1 , wherein the first state machine engine and the second state machine engine are configured to output all zeroes as end padding zero data for any subsequent DDR DMA read cycles when the buffer of the first state machine engine or the buffer of the second state machine engine is empty.

8. The system of claim 7 , wherein the DMA controller is configured to recognize and separate the end padding zero data received from the first state machine engine or the second state machine engine.

Assignments (7)