MEMORY CELL STRUCTURES

1 . A memory cell, comprising:

an interface dielectric adjacent to a semiconductor;

a tunnel dielectric adjacent to the interface dielectric;

a charge trap adjacent to the tunnel dielectric;

a blocking dielectric adjacent to the charge trap;

a control gate adjacent to the blocking dielectric; and

a storage dielectric between the tunnel dielectric and the charge trap.

2 . The memory cell of claim 1 , further comprising an interface metallic between the blocking dielectric and the control gate.

3 . The memory cell of claim 1 , wherein the tunnel dielectric and the blocking dielectric are of the same material.

4 . The memory cell of claim 3 , wherein the blocking dielectric is thicker than the tunnel dielectric.

5 . The memory cell of claim 1 , wherein the interface dielectric is to allow charges to pass therethrough by direct tunneling.

6 . The memory cell of claim 1 , wherein the tunnel dielectric is to accelerate charges from the interface dielectric to the charge trap.

7 . The memory cell of claim 1 , wherein the interface dielectric comprises oxygen-rich silicon oxynitride, the tunnel dielectric comprises hafnium tantalum oxynitride, the charge trap comprises gallium nitride, and the blocking dielectric comprises hafnium tantalum oxynitride.

8 - 23 . (canceled)

24 . The memory cell of claim 1 , wherein the interface dielectric is oxygen-rich silicon oxynitride and is in direct physical contact with the semiconductor.

25 . The memory cell of claim 24 , wherein the interface dielectric is between the semiconductor and the tunnel dielectric.

26 . The memory cell of claim 24 , wherein the tunnel dielectric is in direct physical contact with the interface dielectric.

27 . The memory cell of claim 26 , wherein tunnel dielectric is hafnium tantalum oxynitride.

28 . The memory cell of claim 1 , wherein the tunnel dielectric is thicker than the interface dielectric.

29 . The memory cell of claim 1 , wherein the storage dielectric is injector silicon-rich nitride.

30 . The memory cell of claim 2 , wherein the interface metallic is tantalum nitride.

31 . A method of forming a memory cell, comprising:

forming an interface dielectric adjacent to a semiconductor;

forming a tunnel dielectric adjacent to the interface dielectric;

forming a charge trap adjacent to the tunnel dielectric;

forming a blocking dielectric adjacent to the charge trap;

forming a control gate adjacent to the blocking dielectric; and

forming a storage dielectric between the tunnel dielectric and the charge trap.

32 . The method of claim 31 , further comprising forming an interface metallic between the blocking dielectric and the control gate.

33 . The method of claim 32 , wherein forming the interface metallic between the blocking dielectric and the control gate comprises forming tantalum nitride between the blocking dielectric and the control gate.

34 . The method of claim 31 , wherein forming the interface dielectric adjacent to the semiconductor comprises forming oxygen-rich silicon oxynitride in direct physical contact with the semiconductor.

35 . The method of claim 31 , wherein forming the storage dielectric between the tunnel dielectric and the charge trap comprises forming injector silicon-rich nitride between the tunnel dielectric and the charge trap.