Systems and methods for memory cell array initialization

1. An apparatus comprising:

at least one mode register configured to enable an array reset mode;

a memory cell array including one or more sense amplifiers, each of the one or more sense amplifier including at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line;

control logic coupled to the memory cell array, and in communication with the at least one mode register, the control logic configured to:

drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage, wherein the bit-line precharge voltage corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines,

wherein the at least one mode register is further configured to enable a self-refresh mode, wherein the control logic is further configured to generate, in response to self-refresh mode being enabled, an internal self-refresh pulse internally, wherein the internal self-refresh pulse causes a current row address of the memory cell array to be activated; and

a refresh counter comparator, wherein the at least one mode register further comprises a valid data register, and wherein the refresh counter comparator is configured to set, at a first row address of the refresh counter, the valid data register to a first state indicating that all memory cells of the memory cell array have not been reset, and wherein when the refresh counter outputs the first row address a second time, resetting the valid data register to a second state indicating that all memory cells of the memory cell array have been reset.

2. The apparatus of claim 1 further comprising a refresh counter, wherein the refresh counter is configured to update the current row address to a subsequent row address each time the internal self-refresh pulse is generated.

3. The apparatus of claim 1 , wherein the bit value associated with the bit-line precharge voltage is written to the respective memory cells of the current row address associated with each of the first or second bit lines.

4. The apparatus of claim 1 , wherein the bit-line precharge voltage is one of supply voltage or ground.

5. The apparatus of claim 1 , wherein the sense amplifier further comprises an equilibrate circuit configured to equilibrate signals on the first terminal and second terminal, wherein the control logic is further configured to enable the equilibrate circuit responsive to the first and second terminals being driven to the bit-line precharge voltage.

6. The apparatus of claim 1 , wherein once all memory cells of the memory cell array have been written with the bit value associated with the bit-line precharge voltage; the control logic is configured to disable the bit-line precharge voltage to allow the first and second terminal to return to a nominal bit-line voltage.

7. The apparatus of claim 1 , wherein the same bit values are written to the respective memory cells associated with the first and second bit lines.

8. An apparatus comprising:

control logic configured to:

receive an array reset mode command;

drive, in response to receiving the array reset mode command, each of a first terminal and a second terminal of a sense amplifier to a bit-line precharge voltage, wherein the first terminal is coupled to a first bit-line and the second terminal is coupled to a second bit-line, wherein the bit-line precharge voltage corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines;

generate, in response to receiving the array reset mode command, an internal self-refresh pulse periodically;

activate a current row address indicated by a refresh counter, wherein by activating the current row address, the bit value associated with the bit-line precharge voltage is written to the respective memory cells associated with each of the first and second bit lines at the current row address;

update the current row address of the refresh counter to a subsequent address;

set a valid data register, at a first row address of the refresh counter, to a first state indicating all memory cells of the memory cell array have not been reset; and

set the valid data register, when the refresh counter outputs the first row address a second time, to a second state indicating that all memory cells of the memory cell array have been reset.

9. The apparatus of claim 8 , wherein the control logic is further configured to:

load, in response to receiving the array reset mode command, a mode register, wherein the mode register is configured to enable a bit-line precharge voltage to be applied to the first and second terminals, and to enable an internal self-refresh mode.

10. The apparatus of claim 8 , wherein the bit-line precharge voltage is one of supply voltage or ground.

11. The apparatus of claim 8 , wherein the control logic is further configured to:

equilibrate signals on the first terminal and second terminal responsive to the first and second terminals being driven to the bit-line precharge voltage.

12. The apparatus of claim 1 , wherein once all memory cells of the memory cell array have been written with the bit value associated with the bit-line precharge voltage, the control logic is further configured to disable the bit-line precharge voltage to allow the first and second terminal to return to a nominal bit-line voltage.

13. A method comprising:

receiving an array reset mode command;

enabling an array reset mode responsive, at least in part, to receiving the array reset mode command, wherein enabling an array reset mode comprises at least:

enabling a bit-line precharge voltage;

driving a first terminal of a sense amplifier to the bit-line precharge voltage, wherein the first terminal is coupled to a first bit-line;

driving a second terminal of the sense amplifier to the bit-line precharge voltage, wherein the second terminal is coupled to a second bit-line;

generating a self-refresh pulse;

activating, in response to the self-refresh pulse, a current row address indicated by a refresh counter;

writing a bit value corresponding to the bit-line precharge voltage to respective memory cells associated with at least one of the first and second bit lines at the current row address; and

updating the refresh counter to output a subsequent row address;

setting a valid data register to a first state indicating that all memory cells of a memory cell array have not been reset; and

setting the valid data register to a second state indicating that all memory cells of the memory cell array have been reset.

14. An apparatus comprising:

at least one mode register configured to enable an array reset mode;

a memory cell array including one or more sense amplifiers, each of the one or more sense amplifier including at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line;

control logic coupled to the memory cell array, and in communication with the at least one mode register, the control logic configured to:

drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage, wherein the bit-line precharge voltage corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines,

wherein once all memory cells of the memory cell array have been written with the bit value associated with the bit-line precharge voltage, the control logic is configured to disable the bit-line precharge voltage to allow the first and second terminal to return to a nominal bit-line voltage.

15. An apparatus comprising:

at least one mode register configured to enable an array reset mode;

a memory cell array including one or more sense amplifiers, each of the one or more sense amplifier including at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line; and

control logic coupled to the memory cell array, and in communication with the at least one mode register, the control logic configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage, wherein the bit-line precharge voltage corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines,

wherein once all memory cells of the memory cell array have been written with the bit value associated with the bit-line precharge voltage, the control logic is further configured to disable the bit-line precharge voltage to allow the first and second terminal to return to a nominal bit-line voltage.