IP Library Granted Patent US 10,685,882
Granted Patent B2
US 10,685,882 · App. 15/602,627 · Granted Jun 16, 2020

Methods of forming through substrate interconnects

Inventors: Dave Pratt (Meridian, ID); Andy Perkins (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76898H01L21/02282H01L21/76831
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Quick Facts
Patent No.
US 10,685,882
App. No.
15/602,627
Granted
Jun 16, 2020
Kind
B2
Abstract

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Claims (21)

1. A method of forming a through substrate interconnect sequentially comprising:

providing a semiconductor substrate having a first major side and a second major side and having a conductive bondpad within the substrate, the conductive bondpad having an outermost surface coplanar with an outermost surface of the semiconductor substrate along the second major side, the conductive bond pad being configured to provide a conductive contact with another substrate;

providing a passivation dielectric material over the first major side;

forming a via through the passivation dielectric material into the semiconductor substrate from the first major side to the conductive bondpad;

applying a liquid dielectric to line at least an elevationally outermost portion of sidewalls of the via relative the first major side; and

solidifying the liquid dielectric within the via.

2. The method of claim 1 further comprising forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

3. The method of claim 1 wherein the forming of the via stops on a back-side of the conductive bondpad.

4. The method of claim 1 wherein the first major side is a back-side of the substrate, and the second major side is a front-side of the substrate.

5. The method of claim 1 wherein the first major side is a front-side of the substrate, and the second major side is a back-side of the substrate.

6. The method of claim 1 wherein the applying is conducted in multiple separate liquid dielectric application steps.

7. The method of claim 1 wherein the applying is of spin-on liquid dielectric in a spin-on manner.

8. The method of claim 1 wherein the applying lines all sidewalls of the via with liquid dielectric.

9. The method of claim 1 wherein the applying completely covers a base of the via with liquid dielectric.

10. The method of claim 1 wherein the applying lines all sidewalls of the via with liquid dielectric, and completely covers a base of the via with liquid dielectric.

11. A method of forming a through substrate interconnect, comprising:

forming a via through a passivation dielectric material and a semiconductive material, the via being formed from a first side of the substrate to an innermost surface of a conductive bondpad, the conductive bondpad having an outermost surface that is coplanar with an outermost surface of a second side of the substrate, the conductive bond pad being configured to provide a conductive contact with another substrate;

forming dielectric material along sidewalls of the via and on the first side of the substrate over the passivation dielectric material;

forming conductive material within the via directly against the dielectric material; and wherein the forming the dielectric material comprises applying liquid dielectric material and subsequent solidifying of the liquid dielectric material within the via.

12. The method of claim 11 further comprising etching the solidified dielectric material.

13. The method of claim 11 wherein the forming the via extends the via entirely through the bondpad.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
Continuity (5)
Continuation 14561642 · Dec 5, 2014
Division 14100893 · Dec 9, 2013
Division 13248970 · Sep 29, 2011
Division 11840120 · Aug 16, 2007
Related Publication 20170256452A1 · Sep 7, 2017