IP Library Granted Patent US 9,685,375
Granted Patent B2
US 9,685,375 · App. 14/561,642 · Granted Jun 20, 2017

Methods of forming through substrate interconnects

Inventors: Dave Pratt (Meridian, ID); Andy Perkins (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76898H01L21/02282H01L21/76831
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,685,375
App. No.
14/561,642
Granted
Jun 20, 2017
Kind
B2
Abstract

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Claims (28)

1. A method of forming a through substrate interconnect sequentially comprising:

forming a via into semiconductive material of a semiconductor substrate comprising first and second major sides, the via being formed from the first major side to a conductive bondpad which is more proximate to the second major side than the first major side, the conductive bondpad being exposed along an outermost surface of the second major side;

applying a liquid dielectric over sidewalls of the via, over a base surface of the via comprising the conductive bondpad and over an elevationally outermost surface of the first major side, the applying being conducted in multiple separate applications of liquid dielectric;

solidifying the liquid dielectric within the via and over the elevationally outermost surface of the first major side;

removing all of the solidified dielectric from being over the elevationally outermost surface of the first major side and from over the base surface, the removing comprising anisotropic etching of the solidified dielectric material; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

2. The method of claim 1 wherein the forming of the via stops on a back-side of the conductive bondpad.

3. The method of claim 1 wherein the first major side is a back-side of the substrate, and the second major side is a front-side of the substrate.

4. The method of claim 1 wherein the first major side is a front-side of the substrate, and the second major side is a back-side of the substrate.

5. The method of claim 1 wherein the applying is of spin-on liquid dielectric in a spin-on manner.

6. The method of claim 1 wherein the applying lines all sidewalls of the via with liquid dielectric.

7. The method of claim 1 wherein the applying completely covers a base of the via with liquid dielectric.

8. The method of claim 1 wherein the applying lines all sidewalls of the via with liquid dielectric, and completely covers a base of the via with liquid dielectric.

9. The method of claim 1 comprising vapor depositing a dielectric material to line at least an elevationally outermost portion of the sidewalls of the via before applying the liquid dielectric.

10. The method of claim 9 comprising recessing the dielectric material within the via before applying the liquid dielectric.

11. A method of forming a through substrate interconnect sequentially comprising:

forming a via into semiconductive material of a semiconductor substrate comprising first and second major sides, the via being formed from the first major side to a conductive bondpad which is more proximate to the second major side than the first major side, the conductive bondpad being exposed along an outermost surface of the second major side;

applying a liquid dielectric to line at least an elevationally outermost portion of sidewalls of the via relative the first major side, the applying being conducted in multiple separate applications of liquid dielectric;

solidifying the liquid dielectric within the via; and

forming conductive material within the via over and directly against the solidified dielectric and forming a through substrate interconnect with the conductive material, the conductive material comprising one or more members of the group consisting of doped semiconductive materials, metal alloys and metal compounds.

12. A method of forming a through substrate interconnect sequentially comprising:

forming a via into semiconductive material of a semiconductor substrate comprising first and second major sides, the via being formed from the first major side to a conductive bondpad which is more proximate to the second major side than the first major side, the via being formed to extend into the conductive bondpad, the conductive bondpad being exposed along an outermost surface of the second major side;

applying a liquid dielectric to line at least an elevationally outermost portion of sidewalls of the via relative the first major side, the applying being conducted in multiple separate applications of liquid dielectric;

solidifying the liquid dielectric within the via;

anisotropically etching the solidified dielectric material; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

13. The method of claim 12 comprising forming the via to extend only partially into the conductive bondpad.

14. The method of claim 12 comprising forming the via to extend completely through the conductive bondpad.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (4)
Division 14100893 · Dec 9, 2013
Division 13248970 · Sep 29, 2011
Division 11840120 · Aug 16, 2007
Related Publication 20150087147A1 · Mar 26, 2015