IP Library Granted Patent US 8,629,060
Granted Patent B2
US 8,629,060 · App. 13/248,970 · Granted Jan 14, 2014

Methods of forming through substrate interconnects

Inventors: Dave Pratt (Meridian, ID); Andy Perkins (Boise, ID)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,629,060
App. No.
13/248,970
Granted
Jan 14, 2014
Kind
B2
Abstract

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Claims (50)

1. A method of forming a through substrate interconnect sequentially comprising:

forming a via into a semiconductor substrate, the via extending into semiconductive material of the substrate;

applying a liquid dielectric to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed;

solidifying the liquid dielectric within the via;

depositing a passivation dielectric over the side of the substrate after forming the via and to bridge over the via to leave a void space within the via inward of the passivation dielectric that bridges over the via, none of the bridging passivation dielectric being deposited to within the via;

removing the passivation dielectric from bridging over the via; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

2. The method of claim 1 wherein the applying is of spin-on liquid dielectric in a spin-on manner.

3. The method of claim 1 wherein the applying lines all sidewalls of the via with liquid dielectric.

4. The method of claim 1 wherein the applying completely covers a base of the via with liquid dielectric.

5. The method of claim 1 wherein the applying lines all sidewalls of the via with liquid dielectric, and completely covers a base of the via with liquid dielectric.

6. The method of claim 1 wherein the liquid dielectric is solidified to have a coefficient of thermal expansion which is different from that of the passivation dielectric.

7. A method of forming a through substrate interconnect, comprising:

forming a via into semiconductive material of a semiconductor substrate from a side of the substrate;

applying a liquid dielectric to line at least an elevationally outermost portion of sidewalls of the via;

solidifying the liquid dielectric within the via;

after solidifying the liquid dielectric, forming a passivation dielectric over the substrate side from which the via was formed and to bridge over the via to leave a void space within the via inward of the bridging passivation dielectric, none of the bridging passivation dielectric being formed to within the via;

removing the passivation dielectric from over the via; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

8. The method of claim 7 wherein the removing comprises forming a mask over the passivation dielectric that comprises an opening therethrough to the via and through which the passivation dielectric is removed from over the via by etching.

9. The method of claim 8 wherein the mask comprises a material of different composition as that of the passivation dielectric.

10. The method of claim 7 wherein the applying lines all sidewalls of the via with liquid dielectric.

11. The method of claim 7 wherein the applying completely covers a base of the via with liquid dielectric.

12. A method of forming a through substrate interconnect comprising:

forming a via into a semiconductor substrate, the via extending into semiconductive material of the substrate;

applying a liquid dielectric to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed and forming a bridging passivation dielectric to bridge over the via to leave a void space within the via inward of the bridging passivation dielectric, the bridging passivation dielectric having an arcuate elevationally outermost surface elevationally over the via;

solidifying the liquid dielectric within the via;

removing the bridging passivation dielectric from bridging over the via; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

13. The method of claim 12 wherein the bridging passivation dielectric is within the via, the bridging passivation dielectric that is within the via having an arcuate elevationally innermost surface.

14. The method of claim 13 wherein the arcuate elevationally outermost surface and the arcuate elevationally innermost surface are parallel one another.

15. The method of claim 12 wherein none of the bridging passivation dielectric is deposited to within the via.

16. The method of claim 12 wherein less than all of the sidewalls of the via are lined with liquid dielectric.

17. The method of claim 12 wherein the via extends through less than all of the substrate thereby having a base, the liquid dielectric lining all of the sidewalls and lining only a portion of the base.

18. The method of claim 12 wherein the via extends through less than all of the substrate thereby having a base, the liquid dielectric lining only some of the sidewalls and lining none of the base.

19. A method of forming a through substrate interconnect sequentially comprising:

forming a via into a semiconductor substrate, the via extending into semiconductive material of the substrate;

applying a liquid dielectric to line only an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed;

solidifying the liquid dielectric within the via;

depositing a passivation dielectric over the side of the substrate after forming the via and to within the via;

removing all of the passivation dielectric from within the via; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

20. The method of claim 19 wherein the via extends through less than all of the substrate, the via having a base, none of the base being lined with liquid dielectric.

21. A method of forming a through substrate interconnect sequentially comprising:

forming a via into a semiconductor substrate, the via extending into semiconductive material of the substrate and through less than all of the substrate, the via having a base;

applying a liquid dielectric to line all sidewalls of the via relative a side of the substrate from which the via was initially formed, the liquid dielectric being formed to line only a portion of the base;

solidifying the liquid dielectric within the via;

depositing a passivation dielectric over the side of the substrate after forming the via and to within the via;

removing all of the passivation dielectric from within the via; and

forming conductive material within the via over the solidified dielectric and forming a through substrate interconnect with the conductive material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 11840120 · Aug 16, 2007
Related Publication 20120021601A1 · Jan 26, 2012